diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2015-06-06 13:14:45 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2015-06-06 13:14:45 +0000 |
| commit | e67d1102e0d55effe57427369957351d206f6475 (patch) | |
| tree | ae5222f0b206b4fe1455b6bf791013c65d7bdbb5 /gcc/optabs.h | |
| parent | ad42dbbebaca32f857812b2285c8e4462bb0c688 (diff) | |
| download | gcc-e67d1102e0d55effe57427369957351d206f6475.zip gcc-e67d1102e0d55effe57427369957351d206f6475.tar.gz gcc-e67d1102e0d55effe57427369957351d206f6475.tar.bz2 | |
emit-rtl.c, [...]: Replace rtx base types with more derived ones.
gcc/
* emit-rtl.c, expr.c, gcse.c, optabs.c, optabs.h, print-rtl.c,
rtl.h, bb-reorder.c, builtins.c, calls.c, cfgbuild.c, cfgexpand.c,
cfgrtl.c, cilk-common.c, config/i386/i386.md, cse.c, dwarf2cfi.c,
except.c, final.c, function.c, gcse-common.c, genemit.c,
haifa-sched.c, ifcvt.c, jump.c, loop-invariant.c, loop-iv.c,
lra-constraints.c, lra.c, reload1.c, resource.c, rtlanal.c,
sched-deps.c, sched-ebb.c, sel-sched-ir.c, sel-sched.c,
shrink-wrap.c, stmt.c, store-motion.c: Replace rtx base types with
more derived ones.
From-SVN: r224187
Diffstat (limited to 'gcc/optabs.h')
| -rw-r--r-- | gcc/optabs.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/gcc/optabs.h b/gcc/optabs.h index 8bff2f9..95f5cbc 100644 --- a/gcc/optabs.h +++ b/gcc/optabs.h @@ -377,13 +377,13 @@ rtx emit_conditional_add (rtx, enum rtx_code, rtx, rtx, machine_mode, /* Create but don't emit one rtl instruction to perform certain operations. Modes must match; operands must meet the operation's predicates. Likewise for subtraction and for just copying. */ -extern rtx gen_add2_insn (rtx, rtx); -extern rtx gen_add3_insn (rtx, rtx, rtx); +extern rtx_insn *gen_add2_insn (rtx, rtx); +extern rtx_insn *gen_add3_insn (rtx, rtx, rtx); extern int have_add2_insn (rtx, rtx); -extern rtx gen_addptr3_insn (rtx, rtx, rtx); +extern rtx_insn *gen_addptr3_insn (rtx, rtx, rtx); extern int have_addptr3_insn (rtx, rtx, rtx); -extern rtx gen_sub2_insn (rtx, rtx); -extern rtx gen_sub3_insn (rtx, rtx, rtx); +extern rtx_insn *gen_sub2_insn (rtx, rtx); +extern rtx_insn *gen_sub3_insn (rtx, rtx, rtx); extern int have_sub2_insn (rtx, rtx); /* Return the INSN_CODE to use for an extend operation. */ @@ -391,8 +391,7 @@ extern enum insn_code can_extend_p (machine_mode, machine_mode, int); /* Generate the body of an insn to extend Y (with mode MFROM) into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ -extern rtx gen_extend_insn (rtx, rtx, machine_mode, - machine_mode, int); +extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int); /* Return the insn_code for a FLOAT_EXPR. */ enum insn_code can_float_p (machine_mode, machine_mode, int); @@ -488,7 +487,7 @@ extern void init_tree_optimization_optabs (tree); extern void init_sync_libfuncs (int max); /* Generate a conditional trap instruction. */ -extern rtx gen_cond_trap (enum rtx_code, rtx, rtx, rtx); +extern rtx_insn *gen_cond_trap (enum rtx_code, rtx, rtx, rtx); /* Return true if target supports vector operations for VEC_PERM_EXPR. */ extern bool can_vec_perm_p (machine_mode, bool, const unsigned char *); |