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| author | Uros Bizjak <uros@gcc.gnu.org> | 2013-01-16 08:10:21 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2013-01-16 08:10:21 +0100 |
| commit | 88e784e6c2430ffebd0afd3a31ab6b1f0f5f3ab0 (patch) | |
| tree | 9477e573e8737008d7fa38034cbb5298d49d4610 /gcc/optabs.c | |
| parent | 5147bf6a236993578d316dfe7c7e7182da1cdf90 (diff) | |
| download | gcc-88e784e6c2430ffebd0afd3a31ab6b1f0f5f3ab0.zip gcc-88e784e6c2430ffebd0afd3a31ab6b1f0f5f3ab0.tar.gz gcc-88e784e6c2430ffebd0afd3a31ab6b1f0f5f3ab0.tar.bz2 | |
emit-rtl.c (need_atomic_barrier_p): Mask memory model argument with MEMMODEL_MASK before comparing with MEMMODEL_*...
* emit-rtl.c (need_atomic_barrier_p): Mask memory model argument
with MEMMODEL_MASK before comparing with MEMMODEL_* memory types.
* optabs.c (maybe_emit_sync_lock_test_and_set): Ditto.
(expand_mem_thread_fence): Ditto.
(expand_mem_signal_fence): Ditto.
(expand_atomic_load): Ditto.
(expand_atomic_store): Ditto.
From-SVN: r195228
Diffstat (limited to 'gcc/optabs.c')
| -rw-r--r-- | gcc/optabs.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/optabs.c b/gcc/optabs.c index e637a1e..8a3d3a9 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -7008,9 +7008,9 @@ maybe_emit_sync_lock_test_and_set (rtx target, rtx mem, rtx val, exists, and the memory model is stronger than acquire, add a release barrier before the instruction. */ - if (model == MEMMODEL_SEQ_CST - || model == MEMMODEL_RELEASE - || model == MEMMODEL_ACQ_REL) + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST + || (model & MEMMODEL_MASK) == MEMMODEL_RELEASE + || (model & MEMMODEL_MASK) == MEMMODEL_ACQ_REL) expand_mem_thread_fence (model); if (icode != CODE_FOR_nothing) @@ -7388,7 +7388,7 @@ expand_mem_thread_fence (enum memmodel model) { if (HAVE_mem_thread_fence) emit_insn (gen_mem_thread_fence (GEN_INT (model))); - else if (model != MEMMODEL_RELAXED) + else if ((model & MEMMODEL_MASK) != MEMMODEL_RELAXED) { if (HAVE_memory_barrier) emit_insn (gen_memory_barrier ()); @@ -7412,7 +7412,7 @@ expand_mem_signal_fence (enum memmodel model) { if (HAVE_mem_signal_fence) emit_insn (gen_mem_signal_fence (GEN_INT (model))); - else if (model != MEMMODEL_RELAXED) + else if ((model & MEMMODEL_MASK) != MEMMODEL_RELAXED) { /* By default targets are coherent between a thread and the signal handler running on the same thread. Thus this really becomes a @@ -7467,7 +7467,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) target = gen_reg_rtx (mode); /* For SEQ_CST, emit a barrier before the load. */ - if (model == MEMMODEL_SEQ_CST) + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) expand_mem_thread_fence (model); emit_move_insn (target, mem); @@ -7513,7 +7513,7 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) if (maybe_expand_insn (icode, 2, ops)) { /* lock_release is only a release barrier. */ - if (model == MEMMODEL_SEQ_CST) + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) expand_mem_thread_fence (model); return const0_rtx; } @@ -7540,7 +7540,7 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) emit_move_insn (mem, val); /* For SEQ_CST, also emit a barrier after the store. */ - if (model == MEMMODEL_SEQ_CST) + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) expand_mem_thread_fence (model); return const0_rtx; |