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| author | Kito Cheng <kito.cheng@sifive.com> | 2020-11-11 14:04:34 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-11-18 15:02:22 +0800 |
| commit | b03be74bad08c382da47e048007a78fa3fb4ef49 (patch) | |
| tree | 80fe3a8af8a760238fb992f7859bbc643f428feb /gcc/omp-expand.c | |
| parent | 6a5bb4705fb75fd3afdde938193c59938cc7bfde (diff) | |
| download | gcc-b03be74bad08c382da47e048007a78fa3fb4ef49.zip gcc-b03be74bad08c382da47e048007a78fa3fb4ef49.tar.gz gcc-b03be74bad08c382da47e048007a78fa3fb4ef49.tar.bz2 | |
RISC-V: Support zicsr and zifencei extension for -march.
- CSR related instructions and fence instructions has to be splitted from
baseline ISA, zicsr and zifencei are corresponding sub-extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c (riscv_implied_info):
d and f implied zicsr.
(riscv_ext_flag_table): Handle zicsr and zifencei.
* config/riscv/riscv-opts.h (MASK_ZICSR): New.
(MASK_ZIFENCEI): Ditto.
(TARGET_ZICSR): Ditto.
(TARGET_ZIFENCEI): Ditto.
* config/riscv/riscv.md (clear_cache): Check TARGET_ZIFENCEI.
(fence_i): Ditto.
* config/riscv/riscv.opt (riscv_zi_subext): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-8.c: New.
* gcc.target/riscv/attribute-14.c: Ditto.
Diffstat (limited to 'gcc/omp-expand.c')
0 files changed, 0 insertions, 0 deletions