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| author | Aaron Sawdey <acsawdey@linux.ibm.com> | 2021-03-07 14:47:31 -0600 |
|---|---|---|
| committer | Aaron Sawdey <acsawdey@linux.ibm.com> | 2021-03-08 20:49:47 -0600 |
| commit | 9433c844c8bcf0166567943b45576ceeeee0b131 (patch) | |
| tree | d1bd21491833a82d97d8128f10a8402fc66c752a /gcc/lra-constraints.c | |
| parent | d5d3f15a0e04c30d5dbec09b56c14ad923a3e8da (diff) | |
| download | gcc-9433c844c8bcf0166567943b45576ceeeee0b131.zip gcc-9433c844c8bcf0166567943b45576ceeeee0b131.tar.gz gcc-9433c844c8bcf0166567943b45576ceeeee0b131.tar.bz2 | |
Tighten predicates for p10 ld/cmpi fusion
PR99070 is caused by a fusion pattern matching that the individual
instructions do not match when it is split later. In this case the
ld+cmpi patterns were allowing a d-form load address, which the split
condition would rightly split, however that left us with something that
could not be matched by a ds-form ld instruction, hence the ICE. This
only happened if the target cpu was not power10 -- if we were targeting
power10 then a prefixed pld instruction would get generated because that
can handle d-form. However this is not optimal code either.
So the solution is a new predicate (ds_form_mem_operand) that only
accepts what we can take as for a ds-form load. Then a small
modification of the genfusion.pl script changes the relevant
ld+cmpi patterns to use the new predicate.
gcc/ChangeLog
PR target/99070
* config/rs6000/predicates.md (ds_form_mem_operand) New
predicate.
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10) Use
ds_form_mem_operand in ld/lwa patterns.
* config/rs6000/fusion.md: Regenerate file.
Diffstat (limited to 'gcc/lra-constraints.c')
0 files changed, 0 insertions, 0 deletions