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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-05-01 15:37:52 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-05-01 15:37:52 +0000 |
| commit | 36054fabf5b7b47ffa8c7c6f93c436dd8e8c807c (patch) | |
| tree | 683e38183557a74cc9a0e030ad6dd01a5136bc41 /gcc/lra-constraints.c | |
| parent | 6dce23a8ae9579e12e73201802ef553c13c4f023 (diff) | |
| download | gcc-36054fabf5b7b47ffa8c7c6f93c436dd8e8c807c.zip gcc-36054fabf5b7b47ffa8c7c6f93c436dd8e8c807c.tar.gz gcc-36054fabf5b7b47ffa8c7c6f93c436dd8e8c807c.tar.bz2 | |
[AArch64] Refactor reduc_<su>plus patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_.
* config/aarch64/aarch64-simd-builtins.def
(reduc_splus_): Add new modes.
(reduc_uplus_): New.
* config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove.
(reduc_uplus_v4sf): Likewise.
(reduc_splus_v4sf): Likewise.
(aarch64_addv<mode>): Likewise.
(reduc_uplus_<mode>): Likewise.
(reduc_splus_<mode>): Likewise.
(aarch64_addvv2di): Likewise.
(reduc_uplus_v2di): Likewise.
(reduc_splus_v2di): Likewise.
(aarch64_addvv2si): Likewise.
(reduc_uplus_v2si): Likewise.
(reduc_splus_v2si): Likewise.
(reduc_<sur>plus_<mode>): New.
(reduc_<sur>plus_v2di): Likewise.
(reduc_<sur>plus_v2si): Likewise.
(reduc_<sur>plus_v4sf): Likewise.
(aarch64_addpv4sf): Likewise.
* config/aarch64/arm_neon.h
(vaddv<q>_<s,u,f><8, 16, 32, 64): Rewrite using builtins.
* config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV,
add UNSPEC_SADDV, UNSPEC_UADDV.
(SUADDV): New.
(sur): Add UNSPEC_SADDV, UNSPEC_UADDV.
gcc/testsuite/
* gcc.target/aarch64/vect-vaddv.c: New.
From-SVN: r198500
Diffstat (limited to 'gcc/lra-constraints.c')
0 files changed, 0 insertions, 0 deletions