RISC-V: Implement autovec abs, vneg, vnot.

This patch implements abs<mode>2, vneg<mode>2 and vnot<mode>2
expanders for integer vector registers and adds tests for them.

gcc/ChangeLog:

	* config/riscv/autovec.md (<optab><mode>2): Add vneg/vnot.
	(abs<mode>2): Add.
	* config/riscv/riscv-protos.h (emit_vlmax_masked_mu_insn):
	Declare.
	* config/riscv/riscv-v.cc (emit_vlmax_masked_mu_insn): New
	function.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Add unop tests.
	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/abs-template.h: New test.
	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: New test.
	* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vnot-template.h: New test.

0 files changed, 0 insertions, 0 deletions