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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-10-25 10:25:28 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-10-25 10:25:28 +0000 |
| commit | ad6922b03b0aba8010936394b535acce99f2f66d (patch) | |
| tree | 05acfd94ea6d1113b72ad3ad54100f21c975fa09 /gcc/loop-init.c | |
| parent | 84c20253961be6a343a8fbe3ec14cd46752b4427 (diff) | |
| download | gcc-ad6922b03b0aba8010936394b535acce99f2f66d.zip gcc-ad6922b03b0aba8010936394b535acce99f2f66d.tar.gz gcc-ad6922b03b0aba8010936394b535acce99f2f66d.tar.bz2 | |
With -fpu=neon DI mode shifts are expanded after reload.
With -fpu=neon DI mode shifts are expanded after reload. DI mode registers can
either fully or partially overlap on both ARM and Thumb-2. However the shift
expansion code can only deal with the full overlap case, and generates incorrect
code for partial overlaps. The fix is to add new variants that support either
full overlap or no overlap.
gcc/
PR target/78041
* config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
Remove partial overlap check for shift by 1.
(ashldi3_neon): Likewise.
testsuite/
* gcc.target/arm/pr78041.c: New test.
From-SVN: r241508
Diffstat (limited to 'gcc/loop-init.c')
0 files changed, 0 insertions, 0 deletions