RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori

Sequences of the form "a | C" and "a ^ C" with C being the positive
half of a signed immediate's range with one extra bit set in addition
are mapped to ori/xori and one bseti/binvi to avoid using a temporary
(and a multi-insn sequence to load C into that temporary).

Something similar holds for "a & ~C" being representable as either
bclri + bclri or bclri + andi.

gcc/ChangeLog:

	* config/riscv/bitmanip.md (*<or_optab>i<mode>_extrabit):
	New pattern for binvi+binvi/xori and bseti+bseti/ori
	(*andi<mode>_extrabit): New pattern for bclri+bclri/andi
	* config/riscv/iterators.md (any_or): Match or and ior
	* config/riscv/predicates.md (const_twobits_operand):
	New predicate.
	(uimm_extra_bit_operand): New predicate.
	(uimm_extra_bit_or_twobits): New predicate.
	(not_uimm_extra_bit_operand): New predicate.
	(not_uimm_extra_bit_or_nottwobits): New predicate.
	* config/riscv/riscv.h (UIMM_EXTRA_BIT_OPERAND):
	Helper for the uimm_extra_bit_operand and
	not_uimm_extra_bit_operand predicates.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-bclri.c: Rename
	* gcc.target/riscv/zbs-bclri-01.c: Renamed from above.
	* gcc.target/riscv/zbs-bclri-02.c: New test.
	* gcc.target/riscv/zbs-binvi.c: New test.
	* gcc.target/riscv/zbs-bseti.c: New test.

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