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authorSergei Lewis <slewis@rivosinc.com>2024-06-29 14:34:31 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-06-29 14:36:17 -0600
commit42946aa9b3228262e413481a3193bda85c20ef4b (patch)
tree678f581513f06ce36338a18382313d5441996399 /gcc/jit
parent7682d115402743090f20aca63a3b5e6c205dedff (diff)
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[to-be-committed,RISC-V,V4] movmem for RISCV with V extension
I hadn't updated my repo on the host where I handle email, so it picked up the older version of this patch without the testsuite fix. So, V4 with the testsuite option for lmul fixed. -- And Sergei's movmem patch. Just trivial testsuite adjustment for an option name change and a whitespace fix from me. I've spun this in my tester for rv32 and rv64. I'll wait for pre-commit CI before taking further action. Just a reminder, this patch is designed to handle the case where we can issue a single vector load/store which avoids all the complexities of determining which direction to copy. -- gcc/ChangeLog * config/riscv/riscv.md (movmem<mode>): New expander. gcc/testsuite/ChangeLog PR target/112109 * gcc.target/riscv/rvv/base/movmem-1.c: New test
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