[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

The RISC-V vector machine description relies on the helper function
`sew64_scalar_helper` to emit actual insns for the DI variants of
vssub.vx and vssubu.vx.  This works with vssub.vx, but can cause
problems with vssubu.vx with the scalar operand being constant zero,
because `has_vi_variant_p` returns false, and the operand will be taken
without being loaded into a reg.  The attached testcases can cause an
internal compiler error as a result.

Allowing a constant zero operand in those insns seems to be a simple
solution that only affects minimum existing code.

gcc/ChangeLog:

	* config/riscv/vector.md: Allow zero operand for DI variants of
	vssubu.vx

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vssubu-1.c: New test.
	* gcc.target/riscv/rvv/base/vssubu-2.c: New test.

0 files changed, 0 insertions, 0 deletions