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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-28 11:53:13 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2016-04-28 11:53:13 +0200 |
| commit | 00c072ae51c132e346eab0c6f8c176542efbcd5a (patch) | |
| tree | 146450a4a2fcb549676ac1fec42051bbc2176e40 /gcc/java/decl.c | |
| parent | 174f66220d4d39ed503ded1ec3e7ba514cc4283e (diff) | |
| download | gcc-00c072ae51c132e346eab0c6f8c176542efbcd5a.zip gcc-00c072ae51c132e346eab0c6f8c176542efbcd5a.tar.gz gcc-00c072ae51c132e346eab0c6f8c176542efbcd5a.tar.bz2 | |
[ARC] Add SIMD extensions for ARC HS
gcc/
2016-04-28 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_vector_mode_supported_p): Add support for
the new ARC HS SIMD instructions.
(arc_preferred_simd_mode): New function.
(arc_autovectorize_vector_sizes): Likewise.
(TARGET_VECTORIZE_PREFERRED_SIMD_MODE)
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
(arc_init_reg_tables): Accept new ARC HS SIMD modes.
(arc_init_builtins): Add new SIMD builtin types.
(arc_split_move): Handle 64 bit vector moves.
* config/arc/arc.h (TARGET_PLUS_DMPY, TARGET_PLUS_MACD)
(TARGET_PLUS_QMACW): Define.
* config/arc/builtins.def (QMACH, QMACHU, QMPYH, QMPYHU, DMACH)
(DMACHU, DMPYH, DMPYHU, DMACWH, DMACWHU, VMAC2H, VMAC2HU, VMPY2H)
(VMPY2HU, VADDSUB2H, VSUBADD2H, VADDSUB, VSUBADD, VADDSUB4H)
(VSUBADD4H): New builtins.
* config/arc/simdext.md: Add new ARC HS SIMD instructions.
* testsuite/gcc.target/arc/builtin_simdarc.c: New file.
From-SVN: r235551
Diffstat (limited to 'gcc/java/decl.c')
0 files changed, 0 insertions, 0 deletions