[multiple changes]

2011-03-28  Vladimir Makarov  <vmakarov@redhat.com>

	* ira-color.c (update_left_conflict_sizes_p): Don't assume that
	conflict object hard regset nodes have intersecting hard reg sets.
	
	* regmove.c (regmove_optimize): Move ira_set_pseudo_classes call
	after regstat_init_n_sets_and_refs.

	* ira.c: Add more comments at the top.
	(setup_stack_reg_pressure_class, setup_pressure_classes):
	Add comments how we compute the register pressure classes.
	(setup_allocno_and_important_classes): Add more comments.
	(setup_class_translate_array, reorder_important_classes)
	(setup_reg_class_relations): Add comments.

	* ira-emit.c: Add 2011 to the Copyright line.  Add comments at the
	start of the file.

	* ira-color.c: Add 2011 to the Copyright line.
	(assign_hard_reg):  Add more comments.
	(improve_allocation): Ditto.

	* ira-costs.c: Add 2011 to the Copyright line.
	(setup_cost_classes, setup_regno_cost_classes_by_aclass): Add more
	comments.
	(setup_regno_cost_classes_by_mode): Ditto.

	Initial patches from ira-improv branch:

	2010-08-13  Vladimir Makarov  <vmakarov@redhat.com>

	* ira-build.c: (ira_create_object): Remove initialization of
	OBJECT_PROFITABLE_HARD_REGS.  Initialize OBJECT_ADD_DATA.
	(ira_create_allocno): Remove initialization of
	ALLOCNO_MEM_OPTIMIZED_DEST, ALLOCNO_MEM_OPTIMIZED_DEST_P,
	ALLOCNO_SOMEWHERE_RENAMED_P, ALLOCNO_CHILD_RENAMED_P,
	ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P, ALLOCNO_COLORABLE_P,
	ALLOCNO_NEXT_BUCKET_ALLOCNO, ALLOCNO_PREV_BUCKET_ALLOCNO,
	ALLOCNO_FIRST_COALESCED_ALLOCNO, ALLOCNO_NEXT_COALESCED_ALLOCNO.
	Initialize ALLOCNO_ADD_DATA.
	(copy_info_to_removed_store_destinations): Use ALLOCNO_EMIT_DATA
	and allocno_emit_reg instead of ALLOCNO_MEM_OPTIMIZED_DEST_P and
	ALLOCNO_REG.
	(ira_flattening): Ditto.  Use ALLOCNO_EMIT_DATA instead of
	ALLOCNO_MEM_OPTIMIZED_DEST and ALLOCNO_SOMEWHERE_RENAMED_P.

	* ira.c (ira_reallocate): Remove.
	(setup_pressure_classes): Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost instead of ira_get_register_move_cost.
	(setup_allocno_assignment_flags): Use ALLOCNO_EMIT_DATA.
	(ira): Call ira_initiate_emit_data and ira_finish_emit_data.

	* ira-color.c: Use ALLOCNO_COLOR_DATA instead of
	ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P, ALLOCNO_COLORABLE_P,
	ALLOCNO_AVAILABLE_REGS_NUM, ALLOCNO_NEXT_BUCKET_ALLOCNO,
	ALLOCNO_PREV_BUCKET_ALLOCNO. ALLOCNO_TEMP. Use OBJECT_COLOR_DATA
	instead of OBJECT_PROFITABLE_HARD_REGS, OBJECT_HARD_REGS_NODE,
	OBJECT_HARD_REGS_SUBNODES_START, OBJECT_HARD_REGS_SUBNODES_NUM.
	Fix formatting.
	(object_hard_regs_t, object_hard_regs_node_t): Move from
	ira-int.h.
	(struct object_hard_regs, struct object_hard_regs_node): Ditto.
	(struct allocno_color_data): New.
	(allocno_color_data_t): New typedef.
	(allocno_color_data): New definition.
	(ALLOCNO_COLOR_DATA): New macro.
	(struct object_color_data): New.
	(object_color_data_t): New typedef.
	(object_color_data): New definition.
	(OBJECT_COLOR_DATA): New macro.
	(update_copy_costs, calculate_allocno_spill_cost): Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost instead of ira_get_register_move_cost.
	(move_spill_restore, update_curr_costs): Ditto.
	(allocno_spill_priority): Make it inline.
	(color_pass): Allocate and free allocno_color_dat and
	object_color_data.
	(struct coalesce_data, coalesce_data_t): New.
	(allocno_coalesce_data): New definition.
	(ALLOCNO_COALESCE_DATA): New macro.
	(merge_allocnos, coalesced_allocno_conflict_p): Use
	ALLOCNO_COALESCED_DATA instead of ALLOCNO_FIRST_COALESCED_ALLOCNO,
	ALLOCNO_NEXT_COALESCED_ALLOCNO, ALLOCNO_TEMP.
	(coalesce_allocnos): Ditto.
	(setup_coalesced_allocno_costs_and_nums): Ditto.
	(collect_spilled_coalesced_allocnos): Ditto.
	(slot_coalesced_allocno_live_ranges_intersect_p): Ditto.
	(setup_slot_coalesced_allocno_live_ranges): Ditto.
	(coalesce_spill_slots): Ditto.
	(ira_sort_regnos_for_alter_reg): Ditto.  Allocate, initialize and
	free allocno_coalesce_data.

	* ira-conflicts.c: Fix formatting.
	(process_regs_for_copy): Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost instead of ira_get_register_move_cost.
	(build_object_conflicts): Optimize.

	* ira-costs.c (record_reg_classes): Optimize.  Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost, ira_may_move_in_cost, and
	ira_may_move_out_cost instead of ira_get_register_move_cost and
	ira_get_may_move_cost.
	(record_address_regs): Ditto.
	(scan_one_insn): Optimize.
	(find_costs_and_classes): Optimize.
	(process_bb_node_for_hard_reg_moves): Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost instead of ira_get_register_move_cost.

	* ira-emit.c: Use allocno_emit_reg, ALLOCNO_EMIT_DATA instead of
	ALLOCNO_REG, ALLOCNO_CHILD_RENAMED_P, ALLOCNO_MEM_OPTIMIZED_DEST,
	ALLOCNO_MEM_OPTIMIZED_DEST_P, and ALLOCNO_SOMEWHERE_RENAMED_P.
	(ira_allocno_emit_data, void_p, new_allocno_emit_data_vec): New
	definitions.
	(ira_initiate_emit_data, ira_finish_emit_data)
	(create_new_allocno): New functions.
	(modify_move_list): Call create_new_alloc instead of
	ira_create_allocno.
	(emit_move_list): Call ira_init_register_move_cost_if_necessary.
	Use ira_register_move_cost instead of ira_get_register_move_cost.

	* ira-int.h: Fix some comments.
	(object_hard_regs_t, object_hard_regs_node_t): Move
	to ira-color.c.
	(struct object_hard_regs, struct object_hard_regs_node):
	Ditto.
	(struct ira_object): Remove profitable_hard_regs, hard_regs_node,
	hard_regs_subnodes_start, hard_regs_subnodes_num.  Add new member
	add_data.
	(struct ira_allocno): Make mode and aclass a bitfield.  Move other
	bitfield after mode.  Make hard_regno a short int.  Make
	hard_regno short.  Remove first_coalesced_allocno and
	next_coalesced_allocno.  Move mem_optimized_dest_p,
	somewhere_renamed_p, child_renamed_p, reg, and mem_optimized_dest
	into struct ira_emit_data.  Remove in_graph_p, may_be_spilled_p,
	available_regs_num, next_bucket_allocno, prev_bucket_allocno,
	temp, colorable_p.  Add new member add_data.
	(ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P): Remove.
	(ALLOCNO_COLORABLE_P, ALLOCNO_AVAILABLE_REGS_NUM): Remove.
	(ALLOCNO_NEXT_BUCKET_ALLOCNO, ALLOCNO_PREV_BUCKET_ALLOCNO): Remove.
	(ALLOCNO_TEMP, ALLOCNO_FIRST_COALESCED_ALLOCNO): Remove.
	(ALLOCNO_NEXT_COALESCED_ALLOCNO): Remove.
	(ALLOCNO_ADD_DATA): New macro.
	(ira_emit_data_t): New typedef.
	(struct ira_emit_data): New.  Move mem_optimized_dest_p,
	somewhere_renamed_p, child_renamed_p, reg, mem_optimized_dest
	from struct ira_allocno.
	(ALLOCNO_EMIT_DATA): New macro.
	(ira_allocno_emit_data, allocno_emit_reg): New.
	(ALLOCNO_PROFITABLE_HARD_REGS, OBJECT_HARD_REGS_NODE): Remove.
	(OBJECT_HARD_REGS_SUBNODES_STAR, OBJECT_HARD_REGS_SUBNODES_NUM):
	Remove.
	(OBJECT_ADD_DATA): New macro.
	(ira_reallocate): Remove.
	(ira_initiate_emit_data, ira_finish_emit_data): New.
	(ira_get_register_move_cost, ira_get_may_move_cost): Remove.
	(ira_init_register_move_cost_if_necessary): New.
	(ira_object_conflict_iter_next): Merge into
	ira_object_conflict_iter_cond.
	(FOR_EACH_OBJECT_CONFLICT): Don't use
	ira_object_conflict_iter_next.

	* ira-live.c: (process_single_reg_class_operands): Call
	ira_init_register_move_cost_if_necessary.  Use
	ira_register_move_cost instead of ira_get_register_move_cost.

	2010-08-13  Vladimir Makarov  <vmakarov@redhat.com>

	* ira-int.h (struct target_ira_int): Remove x_cost_classes.

	* ira-costs.c: Fix formatting.
	(cost_classes, cost_classes_num): Remove.
	(struct cost_classes, cost_classes_t, const_cost_classes_t): New.
	(regno_cost_classes, cost_classes_hash, cost_classes_eq): New.
	(cost_classes_del, cost_classes_htab): New.
	(cost_classes_aclass_cache, cost_classes_mode_cache): New.
	(initiate_regno_cost_classes, setup_cost_classes): New.
	(setup_regno_cost_classes_by_aclass): New.
	(setup_regno_cost_classes_by_mode, finish_regno_cost_classes):
	New.
	(record_reg_classes): Use regno_cost_classes instead of
	cost_classes.  Move checking opposite operand up.
	(record_address_regs): Use regno_cost_classes
	instead of cost_classes.
	(scan_one_insn): Ditto.  Use always general register.
	(print_allocno_costs): Use regno_cost_classes instead of
	cost_classes.
	(print_pseudo_costs): Ditto.  Use Reg_N_REFS.
	(find_costs_and_classes): Set up cost classes for each registers.
	Use also their mode for this.  Use regno_cost_classes instead of
	cost_classes.
	(setup_allocno_class_and_costs): Use regno_cost_classes instead of
	cost_classes.
	(free_ira_costs, ira_init_costs): Don't use cost_classes.
	(ira_costs, ira_set_pseudo_classes): Call
	initiate_regno_cost_classes and finish_regno_cost_classes.

	2010-10-04  Vladimir Makarov  <vmakarov@redhat.com>

	* target-def.h (TARGET_IRA_COVER_CLASSES): Remove.

	* target.def (ira_cover_classes): Remove.

	* doc/tm.texi: Remove TARGET_IRA_COVER_CLASSES and
	IRA_COVER_CLASSES.

	* doc/tm.texi.in: Ditto.

	* ira-conflicts.c: Remove mentioning cover classes from the file.
	Use ALLOCNO_CLASS instead of ALLOCNO_COVER_CLASS.  Use
	ALLOCNO_COVER_CLASS_COST instead of ALLOCNO_CLASS_COST.  Fix
	formatting.

	* targhooks.c (default_ira_cover_classes): Remove.

	* targhooks.h (default_ira_cover_classes): Ditto.

	* haifa-sched.c: Remove mentioning cover classes from the file.
	Use ira_reg_pressure_cover instead of ira_reg_class_cover.  Use
	ira_pressure_classes and ira_pressure_classes_num instead of
	ira_reg_class_cover_size and ira_reg_class_cover.  Use
	sched_regno_pressure_class instead of sched_regno_cover_class.
	(mark_regno_birth_or_death, setup_insn_reg_pressure_info): Use
	ira_reg_class_max_nregs instead of ira_reg_class_nregs.

	* ira-int.h: Add 2010 to Copyright.  Remove mentioning cover
	classes from the file.
	(object_hard_regs_t, object_hard_regs_node_t): New typedefs.
	(struct object_hard_regs, struct object_hard_regs_node): New.
	(struct ira_object): New members profitable_hard_regs,
	hard_regs_node, hard_regs_subnodes_start, hard_regs_subnodes_num.
	(struct ira_allocno): Rename cover_class to aclass.  Rename
	cover_class_cost and updated_cover_class_cost to class_cost and
	updated_class_cost.  Remove splay_removed_p and
	left_conflict_size.  Add new members colorable_p.
	(ALLOCNO_SPLAY_REMOVED_P, ALLOCNO_LEFT_CONFLICTS_SIZE): Remove.
	(ALLOCNO_COLORABLE_P): New macro.
	(ALLOCNO_COVER_CLASS): Rename to ALLOCNO_CLASS.
	(ALLOCNO_COVER_CLASS_COST, ALLOCNO_UPDATED_COVER_CLASS_COST):
	Rename to ALLOCNO_CLASS_COST and ALLOCNO_UPDATED__CLASS_COST.
	(OBJECT_...): Rename parameter C to O.
	(OBJECT_PROFITABLE_HARD_REGS): New macro.
	(OBJECT_HARD_REGS_NODE, OBJECT_HARD_REGS_SUBNODES_START)
	(OBJECT_HARD_REGS_SUBNODES_NUM): New macros.
	(struct target_ira_int): New members x_ira_max_memory_move_cost,
	x_ira_max_register_move_cost, x_ira_max_may_move_in_cost,
	x_ira_max_may_move_out_cost, x_ira_reg_allocno_class_p,
	x_ira_reg_pressure_class_p, x_ira_important_class_nums,
	x_ira_reg_class_superunion.  Rename x_prohibited_class_mode_reg to
	x_ira_prohibited_class_mode_reg.  Rename x_ira_reg_class_union to
	x_ira_reg_class_subunion.
	(ira_max_memory_move_cost, ira_max_register_move_cost)
	(ira_max_may_move_in_cost, ira_max_may_move_out_cost)
	(ira_reg_allocno_class_p, ira_reg_pressure_class_p)
	(ira_important_class_nums, ira_reg_class_superunion): New macros.
	(prohibited_class_mode_regs): Rename to
	ira_prohibited_class_mode_regs.
	(ira_reg_class_union): Rename to ira_reg_class_subunion.
	(ira_debug_class_cover): Rename to ira_debug_allocno_classes.
	(ira_set_allocno_cover_class): Rename to ira_set_allocno_class.
	(ira_tune_allocno_costs_and_cover_classes): Rename to
	ira_tune_allocno_costs.
	(ira_debug_hard_regs_forest): New.
	(ira_object_conflict_iter_init, ira_object_conflict_iter_cond)
	(ira_object_conflict_iter_next): Fix comments.
	(ira_hard_reg_set_intersection_p, hard_reg_set_size): New
	functions.
	(ira_allocate_and_set_costs, ira_allocate_and_copy_costs): Rename
	cover_class to aclass.
	(ira_allocate_and_accumulate_costs): Ditto.
	(ira_allocate_and_set_or_copy_costs): Ditto.

	* opts.c (decode_options): Remove ira_cover_class check.

	* ira-color.c: Remove mentioning cover classes from the file.  Use
	ALLOCNO_CLASS, ALLOCNO_CLASS_COST, and ALLOCNO_UPDATED_CLASS_COST
	instead of ALLOCNO_COVER_CLASS, ALLOCNO_COVER_CLASS_COST, and
	ALLOCNO_UPDATED_COVER_CLASS_COST.  Fix formatting.
	(splay-tree.h): Remove include.
	(allocno_coalesced_p, processed_coalesced_allocno_bitmap): Move
	before copy_freq_compare_func.
	(allocnos_for_spilling, removed_splay_allocno_vec): Remove.
	(object_hard_regs_vec, object_hard_regs_htab, node_check_tick):
	New definitions.
	(hard_regs_roots, hard_regs_node_vec): Ditto.
	(object_hard_regs_hash, object_hard_regs_eq, find_hard_regs): Ditto.
	(insert_hard_regs, init_object_hard_regs, add_object_hard_regs): Ditto.
	(finish_object_hard_regs, object_hard_regs_compare): Ditto.
	(create_new_object_hard_regs_node): Ditto.
	(add_new_object_hard_regs_node_to_forest): Ditto.
	(add_object_hard_regs_to_forest, collect_object_hard_regs_cover):
	Ditto.
	(setup_object_hard_regs_nodes_parent, first_common_ancestor_node):
	Ditto.
	(print_hard_reg_set, print_hard_regs_subforest): Ditto.
	(print_hard_regs_forest, ira_debug_hard_regs_forest): Ditto.
	(remove_unused_object_hard_regs_nodes): Ditto.
	(enumerate_object_hard_regs_nodes): Ditto.
	(object_hard_regs_nodes_num, object_hard_regs_nodes): Ditto.
	(object_hard_regs_subnode_t): Ditto.
	(struct object_hard_regs_subnode): Ditto.
	(object_hard_regs_subnodes, object_hard_regs_subnode_index): Ditto.
	(setup_object_hard_regs_subnode_index): Ditto.
	(get_object_hard_regs_subnodes_num): Ditto.
	(form_object_hard_regs_nodes_forest): Ditto.
	(finish_object_hard_regs_nodes_tree): Ditto.
	(finish_object_hard_regs_nodes_forest): Ditto.
	(allocnos_have_intersected_live_ranges_p): Rename to
	allocnos_conflict_by_live_ranges_p.  Move before
	copy_freq_compare_func.
	(pseudos_have_intersected_live_ranges_p): Rename to
	conflict_by_live_ranges_p.  Move before copy_freq_compare_func.
	(setup_left_conflict_sizes_p, update_left_conflict_sizes_p): Ditto.
	(empty_profitable_hard_regs, setup_profitable_hard_regs): Ditto.
	(update_copy_costs): Remove assert.  Skip cost update if the hard
	reg does not belong the class.
	(assign_hard_reg): Process only profitable hard regs.
	(uncolorable_allocnos_num): Make it scalar.
	(allocno_spill_priority): Use ALLOCNO_EXCESS_PRESSURE_POINTS_NUM
	and ira_reg_class_max_nregs instead of ALLOCNO_LEFT_CONFLICTS_SIZE
	and ira_reg_class_max_nregs.
	(bucket_allocno_compare_func): Check frequency first.
	(sort_bucket): Add compare function as a parameter.
	(add_allocno_to_ordered_bucket): Assume no coalesced allocnos.
	(uncolorable_allocnos_splay_tree, USE_SPLAY_P): Remove.
	(push_allocno_to_stack): Rewrite for checking new allocno
	colorability.
	(remove_allocno_from_bucket_and_push): Print cost too.  Remove
	assert.
	(push_only_colorable): Pass new parameter to sort_bucket.
	(push_allocno_to_spill): Remove.
	(allocno_spill_priority_compare): Make it inline and rewrite.
	(splay_tree_allocate, splay_tree_free): Remove.
	(allocno_spill_sort_compare): New function.
	(push_allocnos_to_stack): Sort allocnos for spilling once.  Don't
	build and use splay tree.  Choose first allocno in uncolorable
	allocno bucket to spill.  Remove setting spill cost.
	(all_conflicting_hard_regs): Remove.
	(setup_allocno_available_regs_num): Check only profitable hard
	regs.  Print info about hard regs nodes.
	(setup_allocno_left_conflicts_size): Remove.
	(put_allocno_into_bucket): Don't call
	setup_allocno_left_conflicts_size.  Use
	setup_left_conflict_sizes_p.
	(improve_allocation): New.
	(color_allocnos): Call setup_profitable_hard_regs,
	form_object_hard_regs_nodes_forest, improve_allocation,
	finish_object_hard_regs_nodes_forest.  Setup spill cost.
	(print_loop_title): Use pressure classes.
	(color_allocnso): Ditto.
	(do_coloring): Remove allocation and freeing splay_tree_node_pool
	and allocnos_for_spilling.
	(ira_sort_regnos_for_alter_reg): Don't setup members
	{first,next}_coalesced_allocno.
	(color): Remove allocating and freeing removed_splay_allocno_vec.
	(fast_allocation): Use ira_prohibited_class_mode_regs instead of
	prohibited_class_mode_regs.

	* ira-lives.c: Remove mentioning cover classes from the file.  Fix
	formatting.
	(update_allocno_pressure_excess_length): Use pressure classes.
	(inc_register_pressure, dec_register_pressure): Check for pressure
	class.
	(mark_pseudo_regno_live, mark_pseudo_regno_subword_live): Use
	pressure class.  Use ira_reg_class_nregs instead of
	ira_reg_class_max_nregs.
	(mark_pseudo_regno_dead, mark_pseudo_regno_subword_dead): Ditto.
	(mark_hard_reg_live, mark_hard_reg_dead): Use pressure class.
	(single_reg_class): Use ira_reg_class_nregs instead of
	ira_reg_class_max_nregs.
	(process_bb_node_lives): Use pressure classes.

	* ira-emit.c: Remove mentioning cover classes from the file.  Use
	ALLOCNO_CLASS instead of ALLOCNO_COVER_CLASS.  Fix formatting.
	(change_loop): Use pressure classes.
	(modify_move_list): Call ira_set_allocno_class instead of
	ira_set_allocno_cover_class.

	* ira-build.c: Remove mentioning cover classes from the file.  Use
	ALLOCNO_CLASS and ALLOCNO_CLASS_COST instead of
	ALLOCNO_COVER_CLASS and ALLOCNO_COVER_CLASS_COST.  Use
	ALLOCNO_UPDATED_CLASS_COST instead of
	ALLOCNO_UPDATED_COVER_CLASS_COST.  Fix formatting.
	(ira_create_object): Initiate OBJECT_PROFITABLE_HARD_REGS.
	(ira_create_allocno): Remove initialization of
	ALLOCNO_SPLAY_REMOVED_P, ALLOCNO_LEFT_CONFLICT_SIZE.  Initialize
	ALLOCNO_COLORABLE_P.
	(ira_set_allocno_cover_class): Rename to ira_set_allocno_class.
	Update conflict regs for the objects.
	(create_cap_allocno): Remove assert.  Don't propagate
	ALLOCNO_AVAILABLE_REGS_NUM.
	(ira_free_allocno_costs): New function.
	(finish_allocno): Change a part of code into call of
	ira_free_allocno_costs.
	(low_pressure_loop_node_p): Use pressure classes.
	(object_range_compare_func): Don't compare classes.
	(setup_min_max_conflict_allocno_ids): Ditto.

	* loop-invariant.c: Remove mentioning cover classes from the file.
	Use ira_pressure_classes and ira_pressure_classes_num instead of
	ira_reg_class_cover_size and ira_reg_class_cover.  Fix formatting.
	(get_cover_class_and_nregs): Rename to
	get_cover_pressure_and_nregs.  Use ira_reg_class_max_nregs instead
	of ira_reg_class_nregs.  Use reg_allocno_class instead of
	reg_cover_class.
	(get_inv_cost): Use instead ira_stack_reg_pressure_class of
	STACK_REG_COVER_CLASS.
	(get_regno_cover_class): Rename to get_regno_pressure_class.
	(move_loop_invariants): Initialize and finalize regstat.

	* ira.c: Remove mentioning cover classes from the file.  Add
	comments about coloring without cover classes.  Use ALLOCNO_CLASS
	instead of ALLOCNO_COVER_CLASS.  Fix formatting.
	(alloc_reg_class_subclasses, setup_reg_subclasses): Move it before
	setup_class_subset_and_memory_move_costs.
	(setup_stack_reg_pressure_class, setup_pressure_classes): New.
	(setup_cover_and_important_classes): Rename to
	setup_allocno_and_important_classes.
	(setup_class_translate_array): New.
	(setup_class_translate): Call it for allocno and pressure classes.
	(cover_class_order): Rename to allocno_class_order.
	(comp_reg_classes_func): Use ira_allocno_class_translate instead
	of ira_class_translate.
	(reorder_important_classes): Set up ira_important_class_nums.
	(setup_reg_class_relations): Set up ira_reg_class_superunion.
	(print_class_cover): Rename to print_classes.  Add parameter.
	(ira_debug_class_cover): Rename to ira_debug_allocno_classes.
	Print pressure classes too.
	(find_reg_class_closure): Rename to find_reg_classes.  Don't call
	setup_reg_subclasses.
	(ira_hard_regno_cover_class): Rename to
	ira_hard_regno_allocno_class.
	(ira_reg_class_nregs): Rename to ira_reg_class_max_nregs.
	(setup_prohibited_class_mode_regs): Use
	ira_prohibited_class_mode_regs instead of
	prohibited_class_mode_regs.
	(clarify_prohibited_class_mode_regs): New function.
	(ira_init_register_move_cost): Set up ira_max_register_move_cost,
	ira_max_may_move_in_cost, and ira_max_may_move_out_cost.
	(ira_init_once): Initialize them.
	(free_register_move_costs): Process them.
	(ira_init): Move calls of find_reg_classes and
	setup_hard_regno_aclass after setup_prohibited_class_mode_regs.
	Call clarify_prohibited_class_mode_regs.
	(ira_no_alloc_reg): Remove.
	(too_high_register_pressure_p): Use pressure classes.

	* sched-deps.c: Remove mentioning cover classes from the file.
	Use ira_reg_pressure_cover instead of ira_reg_class_cover.  Use
	ira_pressure_classes and ira_pressure_classes_num instead of
	ira_reg_class_cover_size and ira_reg_class_cover.
	(mark_insn_hard_regno_birth, mark_hard_regno_death): Use
	sched_regno_pressure_class instead of sched_regno_cover_class.
	(mark_insn_pseudo_birth, mark_pseudo_death): Ditto.  Use
	ira_reg_class_max_nregs instead of ira_reg_class_nregs.

	* ira.h: Add 2010 to Copyright.
	(ira_no_alloc_reg): Remove external.
	(struct target_ira): Rename x_ira_hard_regno_cover_class,
	x_ira_reg_class_cover_size, x_ira_reg_class_cover, and
	x_ira_class_translate to x_ira_hard_regno_allocno_class,
	x_ira_allocno_classes_num, x_ira_allocno_classes, and
	x_ira_allocno_class_translate.  Add x_ira_pressure_classes_num,
	x_ira_pressure_classes, x_ira_pressure_class_translate, and
	x_ira_stack_reg_pressure_class.  Rename x_ira_reg_class_nregs to
	x_ira_reg_class_max_nregs.  Add x_ira_reg_class_min_nregs and
	x_ira_no_alloc_regs.
	(ira_hard_regno_cover_class): Rename to
	ira_hard_regno_allocno_class.
	(ira_reg_class_cover_size, ira_reg_class_cover): Rename to
	ira_allocno_classes_num and ira_allocno_classes.
	(ira_class_translate): Rename to ira_allocno_class_translate.
	(ira_pressure_classes_num, ira_pressure_classes): New definitions.
	(ira_pressure_class_translate, ira_stack_reg_pressure_class): Ditto.
	(ira_reg_class_nregs): Rename to ira_reg_class_max_nregs.
	(ira_reg_class_min_nregs, ira_stack_reg_pressure_class): New
	(ira_no_alloc_regs): New.

	* ira-costs.c: Add 2010 to Copyright.  Remove mentioning cover
	classes from the file.  Use ALLOCNO_CLASS instead of
	ALLOCNO_COVER_CLASS.  Use ALLOCNO_CLASS_COST instead of
	ALLOCNO_COVER_CLASS_COST.
	(regno_cover_class): Rename to regno_aclass.
	(record_reg_classes): Use ira_reg_class_subunion instead of
	ira_reg_class_union.
	(record_address_regs): Check overflow.
	(scan_one_insn): Ditto.
	(print_allocno_costs): Print total mem cost fore regional
	allocation.
	(print_pseudo_costs): Use REG_N_REFS.
	(find_costs_and_classes): Use classes intersected with them on the
	1st pass. Check overflow.  Use ira_reg_class_subunion instead of
	ira_reg_class_union.  Use ira_allocno_class_translate and
	regno_aclass instead of ira_class_translate and regno_cover_class.
	Modify code for finding regno_aclass.  Setup preferred classes for
	the next pass.
	(setup_allocno_cover_class_and_costs): Rename to
	setup_allocno_class_and_costs.  Use regno_aclass instead of
	regno_cover_class.  Use ira_set_allocno_class instead of
	ira_set_allocno_cover_class.
	(init_costs, finish_costs): Use regno_aclass instead of
	regno_cover_class.
	(ira_costs): Use setup_allocno_class_and_costs instead of
	setup_allocno_cover_class_and_costs.
	(ira_tune_allocno_costs_and_cover_classes): Rename to
	ira_tune_allocno_costs.  Check overflow.  Skip conflict hard regs
	by processing objects.  Use ira_reg_class_max_nregs instead of
	ira_reg_class_nregs.

	* rtl.h (reg_cover_class): Rename to reg_allocno_class.

	* sched-int.h: Remove mentioning cover classes from the file.
	(sched_regno_cover_class): Rename to sched_regno_pressure_class.

	* reginfo.c: Add 2010 to Copyright.  Remove mentioning cover
	classes from the file.
	(struct reg_pref): Rename coverclass into allocnoclass.
	(reg_cover_class): Rename to reg_allocno_class.

	* Makefile.in (ira-color.o): Remove SPLAY_TREE_H from
	dependencies.

	* config/alpha/alpha.h (IRA_COVER_CLASSES): Remove.

	* config/arm/arm.h (IRA_COVER_CLASSES): Ditto.

	* config/avr/avr.h (IRA_COVER_CLASSES): Ditto.

	* config/bfin/bfin.h (IRA_COVER_CLASSES): Ditto.

	* config/cris/cris.h (IRA_COVER_CLASSES): Ditto.

	* config/fr30/fr30.h (IRA_COVER_CLASSES): Ditto.

	* config/frv/frv.h (IRA_COVER_CLASSES): Ditto.

	* config/h8300/h8300.h (IRA_COVER_CLASSES): Ditto.

	* config/i386/i386.h (STACK_REG_COVER_CLASS): Ditto.

	* config/i386/i386.c (TARGET_IRA_COVER_CLASSES)
	(i386_ira_cover_classes): Ditto.

	* config/ia64/ia64.h (IRA_COVER_CLASSES): Ditto.

	* config/iq2000/iq2000.h (IRA_COVER_CLASSES): Ditto.

	* config/m32r/m32r.h (IRA_COVER_CLASSES): Ditto.

	* config/m68k/m68k.h (IRA_COVER_CLASSES): Ditto.

	* config/mcore/mcore.h (IRA_COVER_CLASSES): Ditto.

	* config/mep/mep.h (IRA_COVER_CLASSES): Ditto.

	* config/mips/mips.c (TARGET_IRA_COVER_CLASSES)
	(mips_ira_cover_classes): Ditto.

	* config/mn10300/mn10300.h (IRA_COVER_CLASSES): Ditto.

	* config/moxie/moxie.h (IRA_COVER_CLASSES): Ditto.

	* config/pa/pa64-regs.h (IRA_COVER_CLASSES): Ditto.

	* config/pa/pa32-regs.h (IRA_COVER_CLASSES): Ditto.

	* config/picochip/picochip.h (IRA_COVER_CLASSES): Ditto.

	* config/rs6000/rs6000.h (IRA_COVER_CLASSES_PRE_VSX)
	(IRA_COVER_CLASSES_VSX): Ditto.

	* config/rs6000/rs6000.c (TARGET_IRA_COVER_CLASSES)
	(rs6000_ira_cover_classes): Ditto.

	* config/rx/rx.h (IRA_COVER_CLASSES): Ditto.

	* config/s390/s390.h (IRA_COVER_CLASSES): Ditto.

	* config/score/score.h (IRA_COVER_CLASSES): Ditto.

	* config/sh/sh.h (IRA_COVER_CLASSES): Ditto.

	* config/sparc/sparc.h (IRA_COVER_CLASSES): Ditto.

	* config/spu/spu.h (IRA_COVER_CLASSES): Ditto.

	* config/stormy16/stormy16.h (IRA_COVER_CLASSES): Ditto.

	* config/v850/v850.h (IRA_COVER_CLASSES): Ditto.

	* config/vax/vax.h (IRA_COVER_CLASSES): Ditto.

	* config/xtensa/xtensa.h (IRA_COVER_CLASSES): Ditto.

From-SVN: r171649

1 files changed, 778 insertions, 343 deletions

diff --git a/gcc/ira.c b/gcc/ira.c
index f2b871f..de7f5b6 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -38,40 +38,51 @@ along with GCC; see the file COPYING3.  If not see
        the other regions.  Therefore data structure representing a
        region is called loop_tree_node.
 
-     o *Cover class* is a register class belonging to a set of
-       non-intersecting register classes containing all of the
-       hard-registers available for register allocation.  The set of
-       all cover classes for a target is defined in the corresponding
-       machine-description file according some criteria.  Such notion
-       is needed because Chaitin-Briggs algorithm works on
-       non-intersected register classes.
+     o *Allocno class* is a register class used for allocation of
+       given allocno.  It means that only hard register of given
+       register class can be assigned to given allocno.  In reality,
+       even smaller subset of (*profitable*) hard registers can be
+       assigned.  In rare cases, the subset can be even smaller
+       because our modification of Chaitin-Briggs algorithm requires
+       that sets of hard registers can be assigned to allocnos forms a
+       forest, i.e. the sets can be ordered in a way where any
+       previous set is not intersected with given set or is a superset
+       of given set.
+
+     o *Pressure class* is a register class belonging to a set of
+       register classes containing all of the hard-registers available
+       for register allocation.  The set of all pressure classes for a
+       target is defined in the corresponding machine-description file
+       according some criteria.  Register pressure is calculated only
+       for pressure classes and it affects some IRA decisions as
+       forming allocation regions.
 
      o *Allocno* represents the live range of a pseudo-register in a
        region.  Besides the obvious attributes like the corresponding
-       pseudo-register number, cover class, conflicting allocnos and
+       pseudo-register number, allocno class, conflicting allocnos and
        conflicting hard-registers, there are a few allocno attributes
        which are important for understanding the allocation algorithm:
 
-       - *Live ranges*.  This is a list of ranges of *program
-         points* where the allocno lives.  Program points represent
-         places where a pseudo can be born or become dead (there are
+       - *Live ranges*.  This is a list of ranges of *program points*
+         where the allocno lives.  Program points represent places
+         where a pseudo can be born or become dead (there are
          approximately two times more program points than the insns)
          and they are represented by integers starting with 0.  The
-         live ranges are used to find conflicts between allocnos of
-         different cover classes.  They also play very important role
-         for the transformation of the IRA internal representation of
-         several regions into a one region representation.  The later is
-         used during the reload pass work because each allocno
-         represents all of the corresponding pseudo-registers.
+         live ranges are used to find conflicts between allocnos.
+         They also play very important role for the transformation of
+         the IRA internal representation of several regions into a one
+         region representation.  The later is used during the reload
+         pass work because each allocno represents all of the
+         corresponding pseudo-registers.
 
        - *Hard-register costs*.  This is a vector of size equal to the
-         number of available hard-registers of the allocno's cover
-         class.  The cost of a callee-clobbered hard-register for an
-         allocno is increased by the cost of save/restore code around
-         the calls through the given allocno's life.  If the allocno
-         is a move instruction operand and another operand is a
-         hard-register of the allocno's cover class, the cost of the
-         hard-register is decreased by the move cost.
+         number of available hard-registers of the allocno class.  The
+         cost of a callee-clobbered hard-register for an allocno is
+         increased by the cost of save/restore code around the calls
+         through the given allocno's life.  If the allocno is a move
+         instruction operand and another operand is a hard-register of
+         the allocno class, the cost of the hard-register is decreased
+         by the move cost.
 
          When an allocno is assigned, the hard-register with minimal
          full cost is used.  Initially, a hard-register's full cost is
@@ -139,12 +150,12 @@ along with GCC; see the file COPYING3.  If not see
        * First, IRA builds regions and creates allocnos (file
          ira-build.c) and initializes most of their attributes.
 
-       * Then IRA finds a cover class for each allocno and calculates
-         its initial (non-accumulated) cost of memory and each
-         hard-register of its cover class (file ira-cost.c).
+       * Then IRA finds an allocno class for each allocno and
+         calculates its initial (non-accumulated) cost of memory and
+         each hard-register of its allocno class (file ira-cost.c).
 
        * IRA creates live ranges of each allocno, calulates register
-         pressure for each cover class in each region, sets up
+         pressure for each pressure class in each region, sets up
          conflict hard registers for each allocno and info about calls
          the allocno lives through (file ira-lives.c).
 
@@ -157,23 +168,63 @@ along with GCC; see the file COPYING3.  If not see
 
        * IRA creates all caps (file ira-build.c).
 
-       * Having live-ranges of allocnos and their cover classes, IRA
-         creates conflicting allocnos of the same cover class for each
-         allocno.  Conflicting allocnos are stored as a bit vector or
-         array of pointers to the conflicting allocnos whatever is
-         more profitable (file ira-conflicts.c).  At this point IRA
-         creates allocno copies.
+       * Having live-ranges of allocnos and their classes, IRA creates
+         conflicting allocnos for each allocno.  Conflicting allocnos
+         are stored as a bit vector or array of pointers to the
+         conflicting allocnos whatever is more profitable (file
+         ira-conflicts.c).  At this point IRA creates allocno copies.
 
      o Coloring.  Now IRA has all necessary info to start graph coloring
        process.  It is done in each region on top-down traverse of the
        region tree (file ira-color.c).  There are following subpasses:
 
+       * Finding profitable hard registers of corresponding allocno
+         class for each allocno.  For example, only callee-saved hard
+         registers are frequently profitable for allocnos living
+         through colors.  If the profitable hard register set of
+         allocno does not form a tree based on subset relation, we use
+         some approximation to form the tree.  This approximation is
+         used to figure out trivial colorability of allocnos.  The
+         approximation is a pretty rare case.
+
        * Putting allocnos onto the coloring stack.  IRA uses Briggs
          optimistic coloring which is a major improvement over
          Chaitin's coloring.  Therefore IRA does not spill allocnos at
          this point.  There is some freedom in the order of putting
          allocnos on the stack which can affect the final result of
-         the allocation.  IRA uses some heuristics to improve the order.
+         the allocation.  IRA uses some heuristics to improve the
+         order.
+	 
+	 We also use a modification of Chaitin-Briggs algorithm which
+         works for intersected register classes of allocnos.  To
+         figure out trivial colorability of allocnos, the mentioned
+         above tree of hard register sets is used.  To get an idea how
+         the algorithm works in i386 example, let us consider an
+         allocno to which any general hard register can be assigned.
+         If the allocno conflicts with eight allocnos to which only
+         EAX register can be assigned, given allocno is still
+         trivially colorable because all conflicting allocnos might be
+         assigned only to EAX and all other general hard registers are
+         still free.
+
+	 To get an idea of the used trivial colorability criterion, it
+	 is also useful to read article "Graph-Coloring Register
+	 Allocation for Irregular Architectures" by Michael D. Smith
+	 and Glen Holloway.  Major difference between the article
+	 approach and approach used in IRA is that Smith's approach
+	 takes register classes only from machine description and IRA
+	 calculate register classes from intermediate code too
+	 (e.g. an explicit usage of hard registers in RTL code for
+	 parameter passing can result in creation of additional
+	 register classes which contain or exclude the hard
+	 registers).  That makes IRA approach useful for improving
+	 coloring even for architectures with regular register files
+	 and in fact some benchmarking shows the improvement for
+	 regular class architectures is even bigger than for irregular
+	 ones.  Another difference is that Smith's approach chooses
+	 intersection of classes of all insn operands in which a given
+	 pseudo occurs.  IRA can use bigger classes if it is still
+	 more profitable than memory usage.
 
        * Popping the allocnos from the stack and assigning them hard
          registers.  If IRA can not assign a hard register to an
@@ -187,6 +238,13 @@ along with GCC; see the file COPYING3.  If not see
          hard-register for the allocno and cost of usage of the
          hard-register for allocnos conflicting with given allocno.
 
+       * Chaitin-Briggs coloring assigns as many pseudos as possible
+         to hard registers.  After coloringh we try to improve
+         allocation with cost point of view.  We improve the
+         allocation by spilling some allocnos and assigning the freed
+         hard registers to other allocnos if it decreases the overall
+         allocation cost.
+
        * After allono assigning in the region, IRA modifies the hard
          register and memory costs for the corresponding allocnos in
          the subregions to reflect the cost of possible loads, stores,
@@ -194,8 +252,8 @@ along with GCC; see the file COPYING3.  If not see
          When default regional allocation algorithm is used
          (-fira-algorithm=mixed), IRA just propagates the assignment
          for allocnos if the register pressure in the region for the
-         corresponding cover class is less than number of available
-         hard registers for given cover class.
+         corresponding pressure class is less than number of available
+         hard registers for given pressure class.
 
      o Spill/restore code moving.  When IRA performs an allocation
        by traversing regions in top-down order, it does not know what
@@ -210,28 +268,29 @@ along with GCC; see the file COPYING3.  If not see
        practice, so there is no real need for a better time complexity
        algorithm.
 
-     o Code change.  After coloring, two allocnos representing the same
-       pseudo-register outside and inside a region respectively may be
-       assigned to different locations (hard-registers or memory).  In
-       this case IRA creates and uses a new pseudo-register inside the
-       region and adds code to move allocno values on the region's
-       borders.  This is done during top-down traversal of the regions
-       (file ira-emit.c).  In some complicated cases IRA can create a
-       new allocno to move allocno values (e.g. when a swap of values
-       stored in two hard-registers is needed).  At this stage, the
-       new allocno is marked as spilled.  IRA still creates the
-       pseudo-register and the moves on the region borders even when
-       both allocnos were assigned to the same hard-register.  If the
-       reload pass spills a pseudo-register for some reason, the
-       effect will be smaller because another allocno will still be in
-       the hard-register.  In most cases, this is better then spilling
-       both allocnos.  If reload does not change the allocation
-       for the two pseudo-registers, the trivial move will be removed
-       by post-reload optimizations.  IRA does not generate moves for
+     o Code change.  After coloring, two allocnos representing the
+       same pseudo-register outside and inside a region respectively
+       may be assigned to different locations (hard-registers or
+       memory).  In this case IRA creates and uses a new
+       pseudo-register inside the region and adds code to move allocno
+       values on the region's borders.  This is done during top-down
+       traversal of the regions (file ira-emit.c).  In some
+       complicated cases IRA can create a new allocno to move allocno
+       values (e.g. when a swap of values stored in two hard-registers
+       is needed).  At this stage, the new allocno is marked as
+       spilled.  IRA still creates the pseudo-register and the moves
+       on the region borders even when both allocnos were assigned to
+       the same hard-register.  If the reload pass spills a
+       pseudo-register for some reason, the effect will be smaller
+       because another allocno will still be in the hard-register.  In
+       most cases, this is better then spilling both allocnos.  If
+       reload does not change the allocation for the two
+       pseudo-registers, the trivial move will be removed by
+       post-reload optimizations.  IRA does not generate moves for
        allocnos assigned to the same hard register when the default
        regional allocation algorithm is used and the register pressure
-       in the region for the corresponding allocno cover class is less
-       than number of available hard registers for given cover class.
+       in the region for the corresponding pressure class is less than
+       number of available hard registers for given pressure class.
        IRA also does some optimizations to remove redundant stores and
        to reduce code duplication on the region borders.
 
@@ -287,6 +346,9 @@ along with GCC; see the file COPYING3.  If not see
    o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
      Register Allocation Based on Graph Fusion.
 
+   o Michael D. Smith and Glenn Holloway.  Graph-Coloring Register
+     Allocation for Irregular Architectures
+
    o Vladimir Makarov. The Integrated Register Allocator for GCC.
 
    o Vladimir Makarov.  The top-down register allocator for irregular
@@ -461,11 +523,53 @@ setup_alloc_regs (bool use_hard_frame_p)
 
 
 
-/* Set up IRA_MEMORY_MOVE_COST, IRA_REGISTER_MOVE_COST.  */
+#define alloc_reg_class_subclasses \
+  (this_target_ira_int->x_alloc_reg_class_subclasses)
+
+/* Initialize the table of subclasses of each reg class.  */
+static void
+setup_reg_subclasses (void)
+{
+  int i, j;
+  HARD_REG_SET temp_hard_regset2;
+
+  for (i = 0; i < N_REG_CLASSES; i++)
+    for (j = 0; j < N_REG_CLASSES; j++)
+      alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
+
+  for (i = 0; i < N_REG_CLASSES; i++)
+    {
+      if (i == (int) NO_REGS)
+	continue;
+
+      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      if (hard_reg_set_empty_p (temp_hard_regset))
+	continue;
+      for (j = 0; j < N_REG_CLASSES; j++)
+	if (i != j)
+	  {
+	    enum reg_class *p;
+
+	    COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
+	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	    if (! hard_reg_set_subset_p (temp_hard_regset,
+					 temp_hard_regset2))
+	      continue;
+	    p = &alloc_reg_class_subclasses[j][0];
+	    while (*p != LIM_REG_CLASSES) p++;
+	    *p = (enum reg_class) i;
+	  }
+    }
+}
+
+
+
+/* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST.  */
 static void
 setup_class_subset_and_memory_move_costs (void)
 {
-  int cl, cl2, mode;
+  int cl, cl2, mode, cost;
   HARD_REG_SET temp_hard_regset2;
 
   for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
@@ -476,34 +580,60 @@ setup_class_subset_and_memory_move_costs (void)
       if (cl != (int) NO_REGS)
 	for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
 	  {
-	    ira_memory_move_cost[mode][cl][0] =
-	      memory_move_cost ((enum machine_mode) mode,
-				(enum reg_class) cl, false);
-	    ira_memory_move_cost[mode][cl][1] =
-	      memory_move_cost ((enum machine_mode) mode,
-				(enum reg_class) cl, true);
+	    ira_max_memory_move_cost[mode][cl][0]
+	      = ira_memory_move_cost[mode][cl][0]
+	      = memory_move_cost ((enum machine_mode) mode,
+				  (enum reg_class) cl, false);
+	    ira_max_memory_move_cost[mode][cl][1]
+	      = ira_memory_move_cost[mode][cl][1]
+	      = memory_move_cost ((enum machine_mode) mode,
+				  (enum reg_class) cl, true);
 	    /* Costs for NO_REGS are used in cost calculation on the
 	       1st pass when the preferred register classes are not
 	       known yet.  In this case we take the best scenario.  */
 	    if (ira_memory_move_cost[mode][NO_REGS][0]
 		> ira_memory_move_cost[mode][cl][0])
-	      ira_memory_move_cost[mode][NO_REGS][0]
+	      ira_max_memory_move_cost[mode][NO_REGS][0]
+		= ira_memory_move_cost[mode][NO_REGS][0]
 		= ira_memory_move_cost[mode][cl][0];
 	    if (ira_memory_move_cost[mode][NO_REGS][1]
 		> ira_memory_move_cost[mode][cl][1])
-	      ira_memory_move_cost[mode][NO_REGS][1]
+	      ira_max_memory_move_cost[mode][NO_REGS][1]
+		= ira_memory_move_cost[mode][NO_REGS][1]
 		= ira_memory_move_cost[mode][cl][1];
 	  }
-      for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
-	{
-	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	  COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
-	  ira_class_subset_p[cl][cl2]
-	    = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
-	}
     }
+  for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+    for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
+      {
+	COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+	AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	ira_class_subset_p[cl][cl2]
+	  = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
+	if (! hard_reg_set_empty_p (temp_hard_regset2)
+	    && hard_reg_set_subset_p (reg_class_contents[cl2],
+				      reg_class_contents[cl]))
+	  for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
+	    {
+	      cost = ira_memory_move_cost[mode][cl2][0];
+	      if (cost > ira_max_memory_move_cost[mode][cl][0])
+		ira_max_memory_move_cost[mode][cl][0] = cost;
+	      cost = ira_memory_move_cost[mode][cl2][1];
+	      if (cost > ira_max_memory_move_cost[mode][cl][1])
+		ira_max_memory_move_cost[mode][cl][1] = cost;
+	    }
+      }
+  for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+    for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
+      {
+	ira_memory_move_cost[mode][cl][0]
+	  = ira_max_memory_move_cost[mode][cl][0];
+	ira_memory_move_cost[mode][cl][1]
+	  = ira_max_memory_move_cost[mode][cl][1];
+      }
+  setup_reg_subclasses ();
 }
 
 
@@ -535,20 +665,6 @@ ira_allocate (size_t len)
   return res;
 }
 
-/* Reallocate memory PTR of size LEN for IRA data.  */
-void *
-ira_reallocate (void *ptr, size_t len)
-{
-  void *res;
-
-#ifndef IRA_NO_OBSTACK
-  res = obstack_alloc (&ira_obstack, len);
-#else
-  res = xrealloc (ptr, len);
-#endif
-  return res;
-}
-
 /* Free memory ADDR allocated for IRA data.  */
 void
 ira_free (void *addr ATTRIBUTE_UNUSED)
@@ -618,120 +734,235 @@ ira_debug_disposition (void)
 }
 
 
-#define alloc_reg_class_subclasses \
-  (this_target_ira_int->x_alloc_reg_class_subclasses)
 
-/* Initialize the table of subclasses of each reg class.  */
+/* Set up ira_stack_reg_pressure_class which is the biggest pressure
+   register class containing stack registers or NO_REGS if there are
+   no stack registers.  To find this class, we iterate through all
+   register pressure classes and choose the first register pressure
+   class containing all the stack registers and having the biggest
+   size.  */
 static void
-setup_reg_subclasses (void)
+setup_stack_reg_pressure_class (void)
+{
+  ira_stack_reg_pressure_class = NO_REGS;
+#ifdef STACK_REGS
+  {
+    int i, best, size;
+    enum reg_class cl;
+    HARD_REG_SET temp_hard_regset2;
+
+    CLEAR_HARD_REG_SET (temp_hard_regset);
+    for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
+      SET_HARD_REG_BIT (temp_hard_regset, i);
+    best = 0;
+    for (i = 0; i < ira_pressure_classes_num; i++)
+      {
+	cl = ira_pressure_classes[i];
+	COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset);
+	AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+	size = hard_reg_set_size (temp_hard_regset2);
+	if (best < size)
+	  {
+	    best = size;
+	    ira_stack_reg_pressure_class = cl;
+	  }
+      }
+  }
+#endif
+}
+
+/* Find pressure classes which are register classes for which we
+   calculate register pressure in IRA, register pressure sensitive
+   insn scheduling, and register pressure sensitive loop invariant
+   motion.
+
+   To make register pressure calculation easy, we always use
+   non-intersected register pressure classes.  A move of hard
+   registers from one register pressure class is not more expensive
+   than load and store of the hard registers.  Most likely an allocno
+   class will be a subset of a register pressure class and in many
+   cases a register pressure class.  That makes usage of register
+   pressure classes a good approximation to find a high register
+   pressure.  */
+static void
+setup_pressure_classes (void)
 {
-  int i, j;
+  int cost, i, n, curr;
+  int cl, cl2;
+  enum reg_class pressure_classes[N_REG_CLASSES];
+  int m;
   HARD_REG_SET temp_hard_regset2;
+  bool insert_p;
 
-  for (i = 0; i < N_REG_CLASSES; i++)
-    for (j = 0; j < N_REG_CLASSES; j++)
-      alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
-
-  for (i = 0; i < N_REG_CLASSES; i++)
+  n = 0;
+  for (cl = 0; cl < N_REG_CLASSES; cl++)
     {
-      if (i == (int) NO_REGS)
+      if (ira_available_class_regs[cl] == 0)
 	continue;
-
-      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
-      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-      if (hard_reg_set_empty_p (temp_hard_regset))
+      /* Check that the moves between any hard registers of the
+	 current class are not more expensive for a legal mode than
+	 load/store of the hard registers of the current class.  Such
+	 class is a potential candidate to be a register pressure
+	 class.  */
+      for (m = 0; m < NUM_MACHINE_MODES; m++)
+	{
+	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	  AND_COMPL_HARD_REG_SET (temp_hard_regset,
+				  ira_prohibited_class_mode_regs[cl][m]);
+	  if (hard_reg_set_empty_p (temp_hard_regset))
+	    continue;
+	  ira_init_register_move_cost_if_necessary ((enum machine_mode) m);
+	  cost = ira_register_move_cost[m][cl][cl];
+	  if (cost <= ira_max_memory_move_cost[m][cl][1]
+	      || cost <= ira_max_memory_move_cost[m][cl][0])
+	    break;
+	}
+      if (m >= NUM_MACHINE_MODES)
 	continue;
-      for (j = 0; j < N_REG_CLASSES; j++)
-	if (i != j)
-	  {
-	    enum reg_class *p;
-
-	    COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
-	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
-	    if (! hard_reg_set_subset_p (temp_hard_regset,
-					 temp_hard_regset2))
+      curr = 0;
+      insert_p = true;
+      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      /* Remove so far added pressure classes which are subset of the
+	 current candidate class.  Prefer GENERAL_REGS as a pressure
+	 register class to another class containing the same
+	 allocatable hard registers.  We do this because machine
+	 dependent cost hooks might give wrong costs for the latter
+	 class but always give the right cost for the former class
+	 (GENERAL_REGS).  */
+      for (i = 0; i < n; i++)
+	{
+	  cl2 = pressure_classes[i];
+	  COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+	  AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	  if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2)
+	      && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2)
+		  || cl2 == (int) GENERAL_REGS))
+	    {
+	      pressure_classes[curr++] = (enum reg_class) cl2;
+	      insert_p = false;
 	      continue;
-	    p = &alloc_reg_class_subclasses[j][0];
-	    while (*p != LIM_REG_CLASSES) p++;
-	    *p = (enum reg_class) i;
-	  }
+	    }
+	  if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)
+	      && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)
+		  || cl == (int) GENERAL_REGS))
+	    continue;
+	  pressure_classes[curr++] = (enum reg_class) cl2;
+	}
+      /* If the current candidate is a subset of a so far added
+	 pressure class, don't add it to the list of the pressure
+	 classes.  */
+      if (insert_p)
+	pressure_classes[curr++] = (enum reg_class) cl;
+      n = curr;
     }
-}
-
-
-
-/* Set the four global variables defined above.  */
+#ifdef ENABLE_IRA_CHECKING
+  /* Check pressure classes correctness: here we check that hard
+     registers from all register pressure classes contains all hard
+     registers available for the allocation.  */
+  CLEAR_HARD_REG_SET (temp_hard_regset);
+  CLEAR_HARD_REG_SET (temp_hard_regset2);
+  for (cl = 0; cl <= LIM_REG_CLASSES; cl++)
+    {
+      for (i = 0; i < n; i++)
+	if ((int) pressure_classes[i] == cl)
+	  break;
+      IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+      if (i >= n)
+	IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+    }
+  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+  AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+  ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
+#endif
+  ira_pressure_classes_num = 0;
+  for (i = 0; i < n; i++)
+    {
+      cl = (int) pressure_classes[i];
+      ira_reg_pressure_class_p[cl] = true;
+      ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl;
+    }
+  setup_stack_reg_pressure_class ();
+}
+
+/* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
+   IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
+
+   Target may have many subtargets and not all target hard regiters can
+   be used for allocation, e.g. x86 port in 32-bit mode can not use
+   hard registers introduced in x86-64 like r8-r15).  Some classes
+   might have the same allocatable hard registers, e.g.  INDEX_REGS
+   and GENERAL_REGS in x86 port in 32-bit mode.  To decrease different
+   calculations efforts we introduce allocno classes which contain
+   unique non-empty sets of allocatable hard-registers.
+
+   Pseudo class cost calculation in ira-costs.c is very expensive.
+   Therefore we are trying to decrease number of classes involved in
+   such calculation.  Register classes used in the cost calculation
+   are called important classes.  They are allocno classes and other
+   non-empty classes whose allocatable hard register sets are inside
+   of an allocno class hard register set.  From the first sight, it
+   looks like that they are just allocno classes.  It is not true.  In
+   example of x86-port in 32-bit mode, allocno classes will contain
+   GENERAL_REGS but not LEGACY_REGS (because allocatable hard
+   registers are the same for the both classes).  The important
+   classes will contain GENERAL_REGS and LEGACY_REGS.  It is done
+   because a machine description insn constraint may refers for
+   LEGACY_REGS and code in ira-costs.c is mostly base on investigation
+   of the insn constraints.  */
 static void
-setup_cover_and_important_classes (void)
+setup_allocno_and_important_classes (void)
 {
   int i, j, n, cl;
   bool set_p;
-  const reg_class_t *cover_classes;
   HARD_REG_SET temp_hard_regset2;
   static enum reg_class classes[LIM_REG_CLASSES + 1];
 
-  if (targetm.ira_cover_classes == NULL)
-    cover_classes = NULL;
-  else
-    cover_classes = targetm.ira_cover_classes ();
-  if (cover_classes == NULL)
-    ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY);
-  else
-    {
-      for (i = 0; (cl = cover_classes[i]) != LIM_REG_CLASSES; i++)
-	classes[i] = (enum reg_class) cl;
-      classes[i] = LIM_REG_CLASSES;
-    }
-
-  if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
+  n = 0;
+  /* Collect classes which contain unique sets of allocatable hard
+     registers.  Prefer GENERAL_REGS to other classes containing the
+     same set of hard registers.  */
+  for (i = 0; i <= LIM_REG_CLASSES; i++)
     {
-      n = 0;
-      for (i = 0; i <= LIM_REG_CLASSES; i++)
+      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      for (j = 0; j < n; j++)
 	{
-	  if (i == NO_REGS)
-	    continue;
-#ifdef CONSTRAINT_NUM_DEFINED_P
-	  for (j = 0; j < CONSTRAINT__LIMIT; j++)
-	    if ((int) REG_CLASS_FOR_CONSTRAINT ((enum constraint_num) j) == i)
-	      break;
-	  if (j < CONSTRAINT__LIMIT)
-	    {
-	      classes[n++] = (enum reg_class) i;
-	      continue;
-	    }
-#endif
-	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	  for (j = 0; j < LIM_REG_CLASSES; j++)
-	    {
-	      if (i == j)
-		continue;
-	      COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
-	      AND_COMPL_HARD_REG_SET (temp_hard_regset2,
-				      no_unit_alloc_regs);
-	      if (hard_reg_set_equal_p (temp_hard_regset,
-					temp_hard_regset2))
-		    break;
-	    }
-	  if (j >= i)
-	    classes[n++] = (enum reg_class) i;
+	  cl = classes[j];
+	  COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+	  AND_COMPL_HARD_REG_SET (temp_hard_regset2,
+				  no_unit_alloc_regs);
+	  if (hard_reg_set_equal_p (temp_hard_regset,
+				    temp_hard_regset2))
+	    break;
 	}
-      classes[n] = LIM_REG_CLASSES;
+      if (j >= n)
+	classes[n++] = (enum reg_class) i;
+      else if (i == GENERAL_REGS)
+	/* Prefer general regs.  For i386 example, it means that
+	   we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
+	   (all of them consists of the same available hard
+	   registers).  */
+	classes[j] = (enum reg_class) i;
     }
+  classes[n] = LIM_REG_CLASSES;
 
-  ira_reg_class_cover_size = 0;
+  /* Set up classes which can be used for allocnos as classes
+     conatining non-empty unique sets of allocatable hard
+     registers.  */
+  ira_allocno_classes_num = 0;
   for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++)
     {
-      for (j = 0; j < i; j++)
-	if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY
-	    && reg_classes_intersect_p ((enum reg_class) cl, classes[j]))
-	  gcc_unreachable ();
       COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
       AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-      if (! hard_reg_set_empty_p (temp_hard_regset))
-	ira_reg_class_cover[ira_reg_class_cover_size++] = (enum reg_class) cl;
+      if (hard_reg_set_empty_p (temp_hard_regset))
+	continue;
+      ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl;
     }
   ira_important_classes_num = 0;
+  /* Add non-allocno classes containing to non-empty set of
+     allocatable hard regs.  */
   for (cl = 0; cl < N_REG_CLASSES; cl++)
     {
       COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
@@ -739,95 +970,86 @@ setup_cover_and_important_classes (void)
       if (! hard_reg_set_empty_p (temp_hard_regset))
 	{
 	  set_p = false;
-	  for (j = 0; j < ira_reg_class_cover_size; j++)
+	  for (j = 0; j < ira_allocno_classes_num; j++)
 	    {
-	      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-	      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	      COPY_HARD_REG_SET (temp_hard_regset2,
-				 reg_class_contents[ira_reg_class_cover[j]]);
+				 reg_class_contents[ira_allocno_classes[j]]);
 	      AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
-	      if ((enum reg_class) cl == ira_reg_class_cover[j]
-		  || hard_reg_set_equal_p (temp_hard_regset,
-					   temp_hard_regset2))
+	      if ((enum reg_class) cl == ira_allocno_classes[j])
 		break;
 	      else if (hard_reg_set_subset_p (temp_hard_regset,
 					      temp_hard_regset2))
 		set_p = true;
 	    }
-	  if (set_p && j >= ira_reg_class_cover_size)
+	  if (set_p && j >= ira_allocno_classes_num)
 	    ira_important_classes[ira_important_classes_num++]
 	      = (enum reg_class) cl;
 	}
     }
-  for (j = 0; j < ira_reg_class_cover_size; j++)
+  /* Now add allocno classes to the important classes.  */
+  for (j = 0; j < ira_allocno_classes_num; j++)
     ira_important_classes[ira_important_classes_num++]
-      = ira_reg_class_cover[j];
-}
-
-/* Set up array IRA_CLASS_TRANSLATE.  */
+      = ira_allocno_classes[j];
+  for (cl = 0; cl < N_REG_CLASSES; cl++)
+    {
+      ira_reg_allocno_class_p[cl] = false;
+      ira_reg_pressure_class_p[cl] = false;
+    }
+  for (j = 0; j < ira_allocno_classes_num; j++)
+    ira_reg_allocno_class_p[ira_allocno_classes[j]] = true;
+  setup_pressure_classes ();
+}
+
+/* Setup translation in CLASS_TRANSLATE of all classes into a class
+   given by array CLASSES of length CLASSES_NUM.  The function is used
+   make translation any reg class to an allocno class or to an
+   pressure class.  This translation is necessary for some
+   calculations when we can use only allocno or pressure classes and
+   such translation represents an approximate representation of all
+   classes.
+
+   The translation in case when allocatable hard register set of a
+   given class is subset of allocatable hard register set of a class
+   in CLASSES is pretty simple.  We use smallest classes from CLASSES
+   containing a given class.  If allocatable hard register set of a
+   given class is not a subset of any corresponding set of a class
+   from CLASSES, we use the cheapest (with load/store point of view)
+   class from CLASSES whose set intersects with given class set */
 static void
-setup_class_translate (void)
+setup_class_translate_array (enum reg_class *class_translate,
+			     int classes_num, enum reg_class *classes)
 {
   int cl, mode;
-  enum reg_class cover_class, best_class, *cl_ptr;
+  enum reg_class aclass, best_class, *cl_ptr;
   int i, cost, min_cost, best_cost;
 
   for (cl = 0; cl < N_REG_CLASSES; cl++)
-    ira_class_translate[cl] = NO_REGS;
+    class_translate[cl] = NO_REGS;
 
-  if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
-    for (cl = 0; cl < LIM_REG_CLASSES; cl++)
-      {
-	COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	for (i = 0; i < ira_reg_class_cover_size; i++)
-	  {
-	    HARD_REG_SET temp_hard_regset2;
-
-	    cover_class = ira_reg_class_cover[i];
-	    COPY_HARD_REG_SET (temp_hard_regset2,
-			       reg_class_contents[cover_class]);
-	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
-	    if (hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2))
-	      ira_class_translate[cl] = cover_class;
-	  }
-      }
-  for (i = 0; i < ira_reg_class_cover_size; i++)
+  for (i = 0; i < classes_num; i++)
     {
-      cover_class = ira_reg_class_cover[i];
-      if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY)
-	for (cl_ptr = &alloc_reg_class_subclasses[cover_class][0];
-	     (cl = *cl_ptr) != LIM_REG_CLASSES;
-	     cl_ptr++)
-	  {
-	    if (ira_class_translate[cl] == NO_REGS)
-	      ira_class_translate[cl] = cover_class;
-#ifdef ENABLE_IRA_CHECKING
-	    else
-	      {
-		COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
-		AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-		if (! hard_reg_set_empty_p (temp_hard_regset))
-		  gcc_unreachable ();
-	      }
-#endif
-	  }
-      ira_class_translate[cover_class] = cover_class;
+      aclass = classes[i];
+      for (cl_ptr = &alloc_reg_class_subclasses[aclass][0];
+	   (cl = *cl_ptr) != LIM_REG_CLASSES;
+	   cl_ptr++)
+	if (class_translate[cl] == NO_REGS)
+	  class_translate[cl] = aclass;
+      class_translate[aclass] = aclass;
     }
-  /* For classes which are not fully covered by a cover class (in
-     other words covered by more one cover class), use the cheapest
-     cover class.  */
+  /* For classes which are not fully covered by one of given classes
+     (in other words covered by more one given class), use the
+     cheapest class.  */
   for (cl = 0; cl < N_REG_CLASSES; cl++)
     {
-      if (cl == NO_REGS || ira_class_translate[cl] != NO_REGS)
+      if (cl == NO_REGS || class_translate[cl] != NO_REGS)
 	continue;
       best_class = NO_REGS;
       best_cost = INT_MAX;
-      for (i = 0; i < ira_reg_class_cover_size; i++)
+      for (i = 0; i < classes_num; i++)
 	{
-	  cover_class = ira_reg_class_cover[i];
+	  aclass = classes[i];
 	  COPY_HARD_REG_SET (temp_hard_regset,
-			     reg_class_contents[cover_class]);
+			     reg_class_contents[aclass]);
 	  AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
 	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	  if (! hard_reg_set_empty_p (temp_hard_regset))
@@ -842,19 +1064,29 @@ setup_class_translate (void)
 		}
 	      if (best_class == NO_REGS || best_cost > min_cost)
 		{
-		  best_class = cover_class;
+		  best_class = aclass;
 		  best_cost = min_cost;
 		}
 	    }
 	}
-      ira_class_translate[cl] = best_class;
+      class_translate[cl] = best_class;
     }
 }
 
-/* Order numbers of cover classes in original target cover class
-   array, -1 for non-cover classes.  This is only live during
-   reorder_important_classes.  */
-static int cover_class_order[N_REG_CLASSES];
+/* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
+   IRA_PRESSURE_CLASS_TRANSLATE.  */
+static void
+setup_class_translate (void)
+{
+  setup_class_translate_array (ira_allocno_class_translate,
+			       ira_allocno_classes_num, ira_allocno_classes);
+  setup_class_translate_array (ira_pressure_class_translate,
+			       ira_pressure_classes_num, ira_pressure_classes);
+}
+
+/* Order numbers of allocno classes in original target allocno class
+   array, -1 for non-allocno classes.  */
+static int allocno_class_order[N_REG_CLASSES];
 
 /* The function used to sort the important classes.  */
 static int
@@ -862,32 +1094,47 @@ comp_reg_classes_func (const void *v1p, const void *v2p)
 {
   enum reg_class cl1 = *(const enum reg_class *) v1p;
   enum reg_class cl2 = *(const enum reg_class *) v2p;
+  enum reg_class tcl1, tcl2;
   int diff;
 
-  cl1 = ira_class_translate[cl1];
-  cl2 = ira_class_translate[cl2];
-  if (cl1 != NO_REGS && cl2 != NO_REGS
-      && (diff = cover_class_order[cl1] - cover_class_order[cl2]) != 0)
+  tcl1 = ira_allocno_class_translate[cl1];
+  tcl2 = ira_allocno_class_translate[cl2];
+  if (tcl1 != NO_REGS && tcl2 != NO_REGS
+      && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0)
     return diff;
   return (int) cl1 - (int) cl2;
 }
 
-/* Reorder important classes according to the order of their cover
-   classes.  */
+/* For correct work of function setup_reg_class_relation we need to
+   reorder important classes according to the order of their allocno
+   classes.  It places important classes containing the same
+   allocatable hard register set adjacent to each other and allocno
+   class with the allocatable hard register set right after the other
+   important classes with the same set.
+
+   In example from comments of function
+   setup_allocno_and_important_classes, it places LEGACY_REGS and
+   GENERAL_REGS close to each other and GENERAL_REGS is after
+   LEGACY_REGS.  */
 static void
 reorder_important_classes (void)
 {
   int i;
 
   for (i = 0; i < N_REG_CLASSES; i++)
-    cover_class_order[i] = -1;
-  for (i = 0; i < ira_reg_class_cover_size; i++)
-    cover_class_order[ira_reg_class_cover[i]] = i;
+    allocno_class_order[i] = -1;
+  for (i = 0; i < ira_allocno_classes_num; i++)
+    allocno_class_order[ira_allocno_classes[i]] = i;
   qsort (ira_important_classes, ira_important_classes_num,
 	 sizeof (enum reg_class), comp_reg_classes_func);
+  for (i = 0; i < ira_important_classes_num; i++)
+    ira_important_class_nums[ira_important_classes[i]] = i;
 }
 
-/* Set up the above reg class relations.  */
+/* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
+   IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
+   IRA_REG_CLASSES_INTERSECT_P.  For the meaning of the relations,
+   please see corresponding comments in ira-int.h.  */
 static void
 setup_reg_class_relations (void)
 {
@@ -912,6 +1159,9 @@ setup_reg_class_relations (void)
 	  if (hard_reg_set_empty_p (temp_hard_regset)
 	      && hard_reg_set_empty_p (temp_set2))
 	    {
+	      /* The both classes have no allocatable hard registers
+		 -- take all class hard registers into account and use
+		 reg_class_subunion and reg_class_superunion.  */
 	      for (i = 0;; i++)
 		{
 		  cl3 = reg_class_subclasses[cl1][i];
@@ -921,7 +1171,8 @@ setup_reg_class_relations (void)
 					  (enum reg_class) cl3))
 		    ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
 		}
-	      ira_reg_class_union[cl1][cl2] = reg_class_subunion[cl1][cl2];
+	      ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2];
+	      ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2];
 	      continue;
 	    }
 	  ira_reg_classes_intersect_p[cl1][cl2]
@@ -929,6 +1180,9 @@ setup_reg_class_relations (void)
 	  if (important_class_p[cl1] && important_class_p[cl2]
 	      && hard_reg_set_subset_p (temp_hard_regset, temp_set2))
 	    {
+	      /* CL1 and CL2 are important classes and CL1 allocatable
+		 hard register set is inside of CL2 allocatable hard
+		 registers -- make CL1 a superset of CL2.  */
 	      enum reg_class *p;
 
 	      p = &ira_reg_class_super_classes[cl1][0];
@@ -937,7 +1191,8 @@ setup_reg_class_relations (void)
 	      *p++ = (enum reg_class) cl2;
 	      *p = LIM_REG_CLASSES;
 	    }
-	  ira_reg_class_union[cl1][cl2] = NO_REGS;
+	  ira_reg_class_subunion[cl1][cl2] = NO_REGS;
+	  ira_reg_class_superunion[cl1][cl2] = NO_REGS;
 	  COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]);
 	  AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
 	  AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
@@ -951,77 +1206,121 @@ setup_reg_class_relations (void)
 	      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	      if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
 		{
+		  /* CL3 allocatable hard register set is inside of
+		     intersection of allocatable hard register sets
+		     of CL1 and CL2.  */
 		  COPY_HARD_REG_SET
 		    (temp_set2,
 		     reg_class_contents[(int)
 					ira_reg_class_intersect[cl1][cl2]]);
 		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 	 	  if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
-		      /* Ignore unavailable hard registers and prefer
-			 smallest class for debugging purposes.  */
+		      /* If the allocatable hard register sets are the
+			 same, prefer GENERAL_REGS or the smallest
+			 class for debugging purposes.  */
 		      || (hard_reg_set_equal_p (temp_hard_regset, temp_set2)
-			  && hard_reg_set_subset_p
-			     (reg_class_contents[cl3],
-			      reg_class_contents
-			      [(int) ira_reg_class_intersect[cl1][cl2]])))
+			  && (cl3 == GENERAL_REGS
+			      || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS
+				  && hard_reg_set_subset_p
+				     (reg_class_contents[cl3],
+				      reg_class_contents
+				      [(int) ira_reg_class_intersect[cl1][cl2]])))))
 		    ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
 		}
 	      if (hard_reg_set_subset_p (temp_hard_regset, union_set))
 		{
+		  /* CL3 allocatbale hard register set is inside of
+		     union of allocatable hard register sets of CL1
+		     and CL2.  */
 		  COPY_HARD_REG_SET
 		    (temp_set2,
-		     reg_class_contents[(int) ira_reg_class_union[cl1][cl2]]);
+		     reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]);
 		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
-	 	  if (ira_reg_class_union[cl1][cl2] == NO_REGS
+	 	  if (ira_reg_class_subunion[cl1][cl2] == NO_REGS
 		      || (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
+			  
+			  && (! hard_reg_set_equal_p (temp_set2,
+						      temp_hard_regset)
+			      || cl3 == GENERAL_REGS
+			      /* If the allocatable hard register sets are the
+				 same, prefer GENERAL_REGS or the smallest
+				 class for debugging purposes.  */
+			      || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS
+				  && hard_reg_set_subset_p
+				     (reg_class_contents[cl3],
+				      reg_class_contents
+				      [(int) ira_reg_class_subunion[cl1][cl2]])))))
+		    ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3;
+		}
+	      if (hard_reg_set_subset_p (union_set, temp_hard_regset))
+		{
+		  /* CL3 allocatable hard register set contains union
+		     of allocatable hard register sets of CL1 and
+		     CL2.  */
+		  COPY_HARD_REG_SET
+		    (temp_set2,
+		     reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]);
+		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+	 	  if (ira_reg_class_superunion[cl1][cl2] == NO_REGS
+		      || (hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 
 			  && (! hard_reg_set_equal_p (temp_set2,
 						      temp_hard_regset)
-			      /* Ignore unavailable hard registers and
-				 prefer smallest class for debugging
-				 purposes.  */
-			      || hard_reg_set_subset_p
-			         (reg_class_contents[cl3],
-				  reg_class_contents
-				  [(int) ira_reg_class_union[cl1][cl2]]))))
-		    ira_reg_class_union[cl1][cl2] = (enum reg_class) cl3;
+			      || cl3 == GENERAL_REGS
+			      /* If the allocatable hard register sets are the
+				 same, prefer GENERAL_REGS or the smallest
+				 class for debugging purposes.  */
+			      || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS
+				  && hard_reg_set_subset_p
+				     (reg_class_contents[cl3],
+				      reg_class_contents
+				      [(int) ira_reg_class_superunion[cl1][cl2]])))))
+		    ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3;
 		}
 	    }
 	}
     }
 }
 
-/* Output all cover classes and the translation map into file F.  */
+/* Output all possible allocno classes and the translation map into
+   file F.  */
 static void
-print_class_cover (FILE *f)
-{
+print_classes (FILE *f, bool pressure_p)
+{
+  int classes_num = (pressure_p
+		     ? ira_pressure_classes_num : ira_allocno_classes_num);
+  enum reg_class *classes = (pressure_p
+			     ? ira_pressure_classes : ira_allocno_classes);
+  enum reg_class *class_translate = (pressure_p
+				     ? ira_pressure_class_translate
+				     : ira_allocno_class_translate);
   static const char *const reg_class_names[] = REG_CLASS_NAMES;
   int i;
 
-  fprintf (f, "Class cover:\n");
-  for (i = 0; i < ira_reg_class_cover_size; i++)
-    fprintf (f, " %s", reg_class_names[ira_reg_class_cover[i]]);
+  fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno");
+  for (i = 0; i < classes_num; i++)
+    fprintf (f, " %s", reg_class_names[classes[i]]);
   fprintf (f, "\nClass translation:\n");
   for (i = 0; i < N_REG_CLASSES; i++)
     fprintf (f, " %s -> %s\n", reg_class_names[i],
-	     reg_class_names[ira_class_translate[i]]);
+	     reg_class_names[class_translate[i]]);
 }
 
-/* Output all cover classes and the translation map into
-   stderr.  */
+/* Output all possible allocno and translation classes and the
+   translation maps into stderr.  */
 void
-ira_debug_class_cover (void)
+ira_debug_allocno_classes (void)
 {
-  print_class_cover (stderr);
+  print_classes (stderr, false);
+  print_classes (stderr, true);
 }
 
-/* Set up different arrays concerning class subsets, cover and
+/* Set up different arrays concerning class subsets, allocno and
    important classes.  */
 static void
-find_reg_class_closure (void)
+find_reg_classes (void)
 {
-  setup_reg_subclasses ();
-  setup_cover_and_important_classes ();
+  setup_allocno_and_important_classes ();
   setup_class_translate ();
   reorder_important_classes ();
   setup_reg_class_relations ();
@@ -1031,77 +1330,158 @@ find_reg_class_closure (void)
 
 /* Set up the array above.  */
 static void
-setup_hard_regno_cover_class (void)
+setup_hard_regno_aclass (void)
 {
   int i;
 
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     {
-      ira_hard_regno_cover_class[i]
+#if 1
+      ira_hard_regno_allocno_class[i]
 	= (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
 	   ? NO_REGS
-	   : ira_class_translate[REGNO_REG_CLASS (i)]);
+	   : ira_allocno_class_translate[REGNO_REG_CLASS (i)]);
+#else
+      int j;
+      enum reg_class cl;
+      ira_hard_regno_allocno_class[i] = NO_REGS;
+      for (j = 0; j < ira_allocno_classes_num; j++)
+ 	{
+	  cl = ira_allocno_classes[j];
+ 	  if (ira_class_hard_reg_index[cl][i] >= 0)
+ 	    {
+	      ira_hard_regno_allocno_class[i] = cl;
+ 	      break;
+ 	    }
+ 	}
+#endif
     }
 }
 
 
 
-/* Form IRA_REG_CLASS_NREGS map.  */
+/* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps.  */
 static void
 setup_reg_class_nregs (void)
 {
-  int cl, m;
+  int i, cl, cl2, m;
 
-  for (cl = 0; cl < N_REG_CLASSES; cl++)
-    for (m = 0; m < MAX_MACHINE_MODE; m++)
-      ira_reg_class_nregs[cl][m] = CLASS_MAX_NREGS ((enum reg_class) cl,
-						    (enum machine_mode) m);
+  for (m = 0; m < MAX_MACHINE_MODE; m++)
+    {
+      for (cl = 0; cl < N_REG_CLASSES; cl++)
+	ira_reg_class_max_nregs[cl][m]
+	  = ira_reg_class_min_nregs[cl][m]
+	  = CLASS_MAX_NREGS ((enum reg_class) cl, (enum machine_mode) m);
+      for (cl = 0; cl < N_REG_CLASSES; cl++)
+	for (i = 0;
+	     (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES;
+	     i++)
+	  if (ira_reg_class_min_nregs[cl2][m]
+	      < ira_reg_class_min_nregs[cl][m])
+	    ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m];
+    }
 }
 
 
 
-/* Set up PROHIBITED_CLASS_MODE_REGS.  */
+/* Set up IRA_PROHIBITED_CLASS_MODE_REGS.  */
 static void
 setup_prohibited_class_mode_regs (void)
 {
-  int i, j, k, hard_regno;
-  enum reg_class cl;
+  int j, k, hard_regno, cl;
 
-  for (i = 0; i < ira_reg_class_cover_size; i++)
+  for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     {
-      cl = ira_reg_class_cover[i];
       for (j = 0; j < NUM_MACHINE_MODES; j++)
 	{
-	  CLEAR_HARD_REG_SET (prohibited_class_mode_regs[cl][j]);
+	  CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]);
 	  for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
 	    {
 	      hard_regno = ira_class_hard_regs[cl][k];
 	      if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j))
-		SET_HARD_REG_BIT (prohibited_class_mode_regs[cl][j],
+		SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
 				  hard_regno);
 	    }
 	}
     }
 }
 
+/* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
+   spanning from one register pressure class to another one.  It is
+   called after defining the pressure classes.  */
+static void
+clarify_prohibited_class_mode_regs (void)
+{
+  int j, k, hard_regno, cl, pclass, nregs;
+
+  for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+    for (j = 0; j < NUM_MACHINE_MODES; j++)
+      for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
+	{
+	  hard_regno = ira_class_hard_regs[cl][k];
+	  if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
+	    continue;
+	  nregs = hard_regno_nregs[hard_regno][j];
+	  pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
+	  for (nregs-- ;nregs >= 0; nregs--)
+	    if (((enum reg_class) pclass
+		 != ira_pressure_class_translate[REGNO_REG_CLASS
+						 (hard_regno + nregs)]))
+	      {
+		SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
+				  hard_regno);
+		break;
+	      }
+	}
+}
+
 
 
 /* Allocate and initialize IRA_REGISTER_MOVE_COST,
-   IRA_MAY_MOVE_IN_COST, and IRA_MAY_MOVE_OUT_COST for MODE if it is
-   not done yet.  */
+   IRA_MAX_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST,
+   IRA_MAY_MOVE_OUT_COST, IRA_MAX_MAY_MOVE_IN_COST, and
+   IRA_MAX_MAY_MOVE_OUT_COST for MODE if it is not done yet.  */
 void
 ira_init_register_move_cost (enum machine_mode mode)
 {
-  int cl1, cl2;
+  int cl1, cl2, cl3;
 
   ira_assert (ira_register_move_cost[mode] == NULL
+	      && ira_max_register_move_cost[mode] == NULL
 	      && ira_may_move_in_cost[mode] == NULL
-	      && ira_may_move_out_cost[mode] == NULL);
+	      && ira_may_move_out_cost[mode] == NULL
+	      && ira_max_may_move_in_cost[mode] == NULL
+	      && ira_max_may_move_out_cost[mode] == NULL);
   if (move_cost[mode] == NULL)
     init_move_cost (mode);
   ira_register_move_cost[mode] = move_cost[mode];
   /* Don't use ira_allocate because the tables exist out of scope of a
      IRA call.  */
+  ira_max_register_move_cost[mode]
+    = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+  memcpy (ira_max_register_move_cost[mode], ira_register_move_cost[mode],
+	  sizeof (move_table) * N_REG_CLASSES);
+  for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
+    {
+      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
+      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      if (hard_reg_set_empty_p (temp_hard_regset))
+	continue;
+      for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
+	if (hard_reg_set_subset_p (reg_class_contents[cl1],
+				   reg_class_contents[cl2]))
+	  for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++)
+	    {
+	      if (ira_max_register_move_cost[mode][cl2][cl3]
+		  < ira_register_move_cost[mode][cl1][cl3])
+		ira_max_register_move_cost[mode][cl2][cl3]
+		  = ira_register_move_cost[mode][cl1][cl3];
+	      if (ira_max_register_move_cost[mode][cl3][cl2]
+		  < ira_register_move_cost[mode][cl3][cl1])
+		ira_max_register_move_cost[mode][cl3][cl2]
+		  = ira_register_move_cost[mode][cl3][cl1];
+	    }
+    }
   ira_may_move_in_cost[mode]
     = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
   memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode],
@@ -1110,14 +1490,36 @@ ira_init_register_move_cost (enum machine_mode mode)
     = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
   memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode],
 	  sizeof (move_table) * N_REG_CLASSES);
+  ira_max_may_move_in_cost[mode]
+    = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+  memcpy (ira_max_may_move_in_cost[mode], ira_max_register_move_cost[mode],
+	  sizeof (move_table) * N_REG_CLASSES);
+  ira_max_may_move_out_cost[mode]
+    = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+  memcpy (ira_max_may_move_out_cost[mode], ira_max_register_move_cost[mode],
+	  sizeof (move_table) * N_REG_CLASSES);
   for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
     {
       for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
 	{
+	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl2]);
+	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	  if (hard_reg_set_empty_p (temp_hard_regset))
+	    continue;
 	  if (ira_class_subset_p[cl1][cl2])
 	    ira_may_move_in_cost[mode][cl1][cl2] = 0;
 	  if (ira_class_subset_p[cl2][cl1])
 	    ira_may_move_out_cost[mode][cl1][cl2] = 0;
+	  if (ira_class_subset_p[cl1][cl2])
+	    ira_max_may_move_in_cost[mode][cl1][cl2] = 0;
+	  if (ira_class_subset_p[cl2][cl1])
+	    ira_max_may_move_out_cost[mode][cl1][cl2] = 0;
+	  ira_register_move_cost[mode][cl1][cl2]
+	    = ira_max_register_move_cost[mode][cl1][cl2];
+	  ira_may_move_in_cost[mode][cl1][cl2]
+	    = ira_max_may_move_in_cost[mode][cl1][cl2];
+	  ira_may_move_out_cost[mode][cl1][cl2]
+	    = ira_max_may_move_out_cost[mode][cl1][cl2];
 	}
     }
 }
@@ -1135,14 +1537,18 @@ ira_init_once (void)
   for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
     {
       ira_register_move_cost[mode] = NULL;
+      ira_max_register_move_cost[mode] = NULL;
       ira_may_move_in_cost[mode] = NULL;
       ira_may_move_out_cost[mode] = NULL;
+      ira_max_may_move_in_cost[mode] = NULL;
+      ira_max_may_move_out_cost[mode] = NULL;
     }
   ira_init_costs_once ();
 }
 
-/* Free ira_register_move_cost, ira_may_move_in_cost, and
-   ira_may_move_out_cost for each mode.  */
+/* Free ira_max_register_move_cost, ira_may_move_in_cost,
+   ira_may_move_out_cost, ira_max_may_move_in_cost, and
+   ira_max_may_move_out_cost for each mode.  */
 static void
 free_register_move_costs (void)
 {
@@ -1150,13 +1556,22 @@ free_register_move_costs (void)
 
   for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
     {
+      if (ira_max_register_move_cost[mode] != NULL)
+	free (ira_max_register_move_cost[mode]);
       if (ira_may_move_in_cost[mode] != NULL)
 	free (ira_may_move_in_cost[mode]);
       if (ira_may_move_out_cost[mode] != NULL)
 	free (ira_may_move_out_cost[mode]);
+      if (ira_max_may_move_in_cost[mode] != NULL)
+	free (ira_max_may_move_in_cost[mode]);
+      if (ira_max_may_move_out_cost[mode] != NULL)
+	free (ira_max_may_move_out_cost[mode]);
       ira_register_move_cost[mode] = NULL;
+      ira_max_register_move_cost[mode] = NULL;
       ira_may_move_in_cost[mode] = NULL;
       ira_may_move_out_cost[mode] = NULL;
+      ira_max_may_move_in_cost[mode] = NULL;
+      ira_max_may_move_out_cost[mode] = NULL;
     }
 }
 
@@ -1169,10 +1584,11 @@ ira_init (void)
   setup_reg_mode_hard_regset ();
   setup_alloc_regs (flag_omit_frame_pointer != 0);
   setup_class_subset_and_memory_move_costs ();
-  find_reg_class_closure ();
-  setup_hard_regno_cover_class ();
   setup_reg_class_nregs ();
   setup_prohibited_class_mode_regs ();
+  find_reg_classes ();
+  clarify_prohibited_class_mode_regs ();
+  setup_hard_regno_aclass ();
   ira_init_costs ();
 }
 
@@ -1271,10 +1687,6 @@ ira_bad_reload_regno (int regno, rtx in, rtx out)
 	  || ira_bad_reload_regno_1 (regno, out));
 }
 
-/* Function specific hard registers that can not be used for the
-   register allocation.  */
-HARD_REG_SET ira_no_alloc_regs;
-
 /* Return TRUE if *LOC contains an asm.  */
 static int
 insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
@@ -1497,17 +1909,32 @@ setup_reg_renumber (void)
 	ALLOCNO_ASSIGNED_P (a) = true;
       ira_free_allocno_updated_costs (a);
       hard_regno = ALLOCNO_HARD_REGNO (a);
-      regno = (int) REGNO (ALLOCNO_REG (a));
+      regno = ALLOCNO_REGNO (a);
       reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno);
-      if (hard_regno >= 0 && ALLOCNO_CALLS_CROSSED_NUM (a) != 0
-	  && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
-					  call_used_reg_set))
+      if (hard_regno >= 0)
 	{
-	  ira_assert (!optimize || flag_caller_saves
-		      || regno >= ira_reg_equiv_len
-		      || ira_reg_equiv_const[regno]
-		      || ira_reg_equiv_invariant_p[regno]);
-	  caller_save_needed = 1;
+	  int i, nwords;
+	  enum reg_class pclass;
+	  ira_object_t obj;
+	  
+	  pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
+	  nwords = ALLOCNO_NUM_OBJECTS (a);
+	  for (i = 0; i < nwords; i++)
+	    {
+	      obj = ALLOCNO_OBJECT (a, i);
+	      IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj),
+				      reg_class_contents[pclass]);
+	    }
+	  if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0
+	      && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
+					      call_used_reg_set))
+	    {
+	      ira_assert (!optimize || flag_caller_saves
+			  || regno >= ira_reg_equiv_len
+			  || ira_reg_equiv_const[regno]
+			  || ira_reg_equiv_invariant_p[regno]);
+	      caller_save_needed = 1;
+	    }
 	}
     }
 }
@@ -1535,13 +1962,13 @@ setup_allocno_assignment_flags (void)
 	 allocnos because the cost info and info about intersected
 	 calls are incorrect for them.  */
       ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0
-				|| ALLOCNO_MEM_OPTIMIZED_DEST_P (a)
+				|| ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p
 				|| (ALLOCNO_MEMORY_COST (a)
-				    - ALLOCNO_COVER_CLASS_COST (a)) < 0);
+				    - ALLOCNO_CLASS_COST (a)) < 0);
       ira_assert (hard_regno < 0
 		  || ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
 						  reg_class_contents
-						  [ALLOCNO_COVER_CLASS (a)]));
+						  [ALLOCNO_CLASS (a)]));
     }
 }
 
@@ -1561,7 +1988,7 @@ calculate_allocation_cost (void)
       ira_assert (hard_regno < 0
 		  || ! ira_hard_reg_not_in_set_p
 		       (hard_regno, ALLOCNO_MODE (a),
-			reg_class_contents[ALLOCNO_COVER_CLASS (a)]));
+			reg_class_contents[ALLOCNO_CLASS (a)]));
       if (hard_regno < 0)
 	{
 	  cost = ALLOCNO_MEMORY_COST (a);
@@ -1571,12 +1998,12 @@ calculate_allocation_cost (void)
 	{
 	  cost = (ALLOCNO_HARD_REG_COSTS (a)
 		  [ira_class_hard_reg_index
-		   [ALLOCNO_COVER_CLASS (a)][hard_regno]]);
+		   [ALLOCNO_CLASS (a)][hard_regno]]);
 	  ira_reg_cost += cost;
 	}
       else
 	{
-	  cost = ALLOCNO_COVER_CLASS_COST (a);
+	  cost = ALLOCNO_CLASS_COST (a);
 	  ira_reg_cost += cost;
 	}
       ira_overall_cost += cost;
@@ -1768,7 +2195,7 @@ setup_preferred_alternate_classes_for_new_pseudos (int start)
       ira_assert (i != old_regno);
       setup_reg_classes (i, reg_preferred_class (old_regno),
 			 reg_alternate_class (old_regno),
-			 reg_cover_class (old_regno));
+			 reg_allocno_class (old_regno));
       if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
 	fprintf (ira_dump_file,
 		 "    New r%d: setting preferred %s, alternative %s\n",
@@ -1798,12 +2225,12 @@ static bool
 too_high_register_pressure_p (void)
 {
   int i;
-  enum reg_class cover_class;
+  enum reg_class pclass;
 
-  for (i = 0; i < ira_reg_class_cover_size; i++)
+  for (i = 0; i < ira_pressure_classes_num; i++)
     {
-      cover_class = ira_reg_class_cover[i];
-      if (ira_loop_tree_root->reg_pressure[cover_class] > 10000)
+      pclass = ira_pressure_classes[i];
+      if (ira_loop_tree_root->reg_pressure[pclass] > 10000)
 	return true;
     }
   return false;
@@ -2015,9 +2442,10 @@ equiv_init_movable_p (rtx x, int regno)
       return 0;
 
     case REG:
-      return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
-	      && reg_equiv[REGNO (x)].replace)
-	     || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0));
+      return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
+	       && reg_equiv[REGNO (x)].replace)
+	      || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS
+		  && ! rtx_varies_p (x, 0)));
 
     case UNSPEC_VOLATILE:
       return 0;
@@ -2050,7 +2478,8 @@ equiv_init_movable_p (rtx x, int regno)
   return 1;
 }
 
-/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true.  */
+/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
+   true.  */
 static int
 contains_replace_regs (rtx x)
 {
@@ -2198,7 +2627,8 @@ memref_used_between_p (rtx memref, rtx start, rtx end)
    assignment - a SET, CLOBBER or REG_INC note.  It is currently not used,
    but needs to be there because this function is called from note_stores.  */
 static void
-no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
+no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED,
+	  void *data ATTRIBUTE_UNUSED)
 {
   int regno;
   rtx list;
@@ -2243,12 +2673,13 @@ adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data)
 static int recorded_label_ref;
 
 /* Find registers that are equivalent to a single value throughout the
-   compilation (either because they can be referenced in memory or are set once
-   from a single constant).  Lower their priority for a register.
+   compilation (either because they can be referenced in memory or are
+   set once from a single constant).  Lower their priority for a
+   register.
 
-   If such a register is only referenced once, try substituting its value
-   into the using insn.  If it succeeds, we can eliminate the register
-   completely.
+   If such a register is only referenced once, try substituting its
+   value into the using insn.  If it succeeds, we can eliminate the
+   register completely.
 
    Initialize the REG_EQUIV_INIT array of initializing insns.
 
@@ -3191,6 +3622,8 @@ ira (FILE *f)
 
   ira_max_point_before_emit = ira_max_point;
 
+  ira_initiate_emit_data ();
+
   ira_emit (loops_p);
 
   if (ira_conflicts_p)
@@ -3223,6 +3656,8 @@ ira (FILE *f)
 	}
     }
 
+  ira_finish_emit_data ();
+
   setup_reg_renumber ();
 
   calculate_allocation_cost ();