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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-09-09 17:59:14 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-09 17:59:14 +0000 |
| commit | dc333d8ff60909dbed89126443e3024f1592f8a4 (patch) | |
| tree | 8cb63764fe33068c8b53a63d5441237984aa4aa7 /gcc/ira.c | |
| parent | 50b3f54d551787e0a066451ef60ef3b055a893e6 (diff) | |
| download | gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.zip gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.tar.gz gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.tar.bz2 | |
Remove AND_HARD_REG_SET
Use "x &= y" instead of "AND_HARD_REG_SET (x, y)" (or just "x & y"
if the result is a temporary).
2019-09-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* hard-reg-set.h (HARD_REG_SET::operator&): New function.
(HARD_REG_SET::operator&): Likewise.
(AND_HARD_REG_SET): Delete.
* caller-save.c (setup_save_areas): Use "&" instead of
AND_HARD_REG_SET.
(save_call_clobbered_regs): Likewise.
* config/gcn/gcn.c (gcn_md_reorg): Likewise.
* config/m32c/m32c.c (reduce_class): Likewise.
* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
* final.c (get_call_reg_set_usage): Likewise.
* ira-color.c (add_allocno_hard_regs_to_forest): Likewise.
(setup_left_conflict_sizes_p): Likewise.
* ira-conflicts.c (print_allocno_conflicts): Likewise.
(ira_build_conflicts): Likewise.
* ira-costs.c (restrict_cost_classes): Likewise.
* ira.c (setup_stack_reg_pressure_class, setup_class_translate_array)
(setup_reg_class_relations): Likewise.
* reginfo.c (init_reg_sets_1, record_subregs_of_mode): Likewise.
* reload1.c (maybe_fix_stack_asms, finish_spills): Likewise.
* resource.c (find_dead_or_set_registers): Likewise.
* sel-sched.c (mark_unavailable_hard_regs): Likewise.
From-SVN: r275530
Diffstat (limited to 'gcc/ira.c')
| -rw-r--r-- | gcc/ira.c | 11 |
1 files changed, 5 insertions, 6 deletions
@@ -757,8 +757,7 @@ setup_stack_reg_pressure_class (void) for (i = 0; i < ira_pressure_classes_num; i++) { cl = ira_pressure_classes[i]; - temp_hard_regset2 = temp_hard_regset; - AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); + temp_hard_regset2 = temp_hard_regset & reg_class_contents[cl]; size = hard_reg_set_size (temp_hard_regset2); if (best < size) { @@ -1117,8 +1116,8 @@ setup_class_translate_array (enum reg_class *class_translate, for (i = 0; i < classes_num; i++) { aclass = classes[i]; - temp_hard_regset = reg_class_contents[aclass]; - AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); + temp_hard_regset = (reg_class_contents[aclass] + & reg_class_contents[cl]); AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); if (! hard_reg_set_empty_p (temp_hard_regset)) { @@ -1262,8 +1261,8 @@ setup_reg_class_relations (void) } ira_reg_class_subunion[cl1][cl2] = NO_REGS; ira_reg_class_superunion[cl1][cl2] = NO_REGS; - intersection_set = reg_class_contents[cl1]; - AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); + intersection_set = (reg_class_contents[cl1] + & reg_class_contents[cl2]); AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); union_set = reg_class_contents[cl1]; IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); |