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| author | Anatoly Sokolov <aesok@post.ru> | 2010-09-02 18:29:37 +0400 |
|---|---|---|
| committer | Anatoly Sokolov <aesok@gcc.gnu.org> | 2010-09-02 18:29:37 +0400 |
| commit | 07b8f0a812a056b69fcaf00bde67aa74b5b02397 (patch) | |
| tree | 8800ae6420f6689c40bea9995085ad6bf47c0f65 /gcc/ira.c | |
| parent | 844022b747eebc8f02c0e7b4165cc10b7521432e (diff) | |
| download | gcc-07b8f0a812a056b69fcaf00bde67aa74b5b02397.zip gcc-07b8f0a812a056b69fcaf00bde67aa74b5b02397.tar.gz gcc-07b8f0a812a056b69fcaf00bde67aa74b5b02397.tar.bz2 | |
target.def (class_likely_spilled_p): New hook.
* target.def (class_likely_spilled_p): New hook.
* doc/tm.texi.in (TARGET_CLASS_LIKELY_SPILLED_P): Document.
* doc/tm.texi: Regenerate.
* targhooks.c (default_class_likely_spilled_p): New function.
* targhooks.h (default_class_likely_spilled_p): Declare.
* regs.h (CLASS_LIKELY_SPILLED_P): Remove.
* combine.c: (cant_combine_insn_p, likely_spilled_retval_p): Use
TARGET_CLASS_LIKELY_SPILLED_P target hook. Use HARD_REGISTER_P macro.
Use fixed_reg_set instead of fixed_regs.
* cse.c (hash_rtx_cb): Use TARGET_CLASS_LIKELY_SPILLED_P target hook.
* calls.c (avoid_likely_spilled_reg): Ditto.
* ira-conflicts.c: (ira_build_conflicts): Ditto.
* ira.c (update_equiv_regs): Ditto.
* mode-switching.c (create_pre_exit): Ditto.
* regmove.c (find_matches): Ditto.
(regclass_compatible_p): Use TARGET_CLASS_LIKELY_SPILLED_P target
hook.
* reload.c (SMALL_REGISTER_CLASS_P): Remove macro.
(small_register_class_p): New inline function.
(push_secondary_reload, find_reusable_reload, find_reloads): Use
small_register_class_p instead of SMALL_REGISTER_CLASS_P.
* config/i386/i386.h (CLASS_LIKELY_SPILLED_P): Remove.
* config/i386/i386.c (ix86_class_likely_spilled_p): New.
(TARGET_CLASS_LIKELY_SPILLED_P): Define.
From-SVN: r163779
Diffstat (limited to 'gcc/ira.c')
| -rw-r--r-- | gcc/ira.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -2363,7 +2363,7 @@ update_equiv_regs (void) if (!REG_P (dest) || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER || reg_equiv[regno].init_insns == const0_rtx - || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) + || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) { /* This might be setting a SUBREG of a pseudo, a pseudo that is |