Remove COPY_HARD_REG_SET

This patch replaces "COPY_HARD_REG_SET (x, y)" with "x = y".

2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* hard-reg-set.h (COPY_HARD_REG_SET): Delete.
	* caller-save.c (save_call_clobbered_regs): Use assignment instead
	of COPY_HARD_REG_SET.
	* config/epiphany/epiphany.c (epiphany_compute_frame_size): Likewise.
	(epiphany_conditional_register_usage): Likewise.
	* config/frv/frv.c (frv_ifcvt_modify_tests): Likewise.
	* config/gcn/gcn.c (gcn_md_reorg): Likewise.
	* config/ia64/ia64.c (ia64_compute_frame_size): Likewise.
	* config/m32c/m32c.c (m32c_register_move_cost): Likewise.
	* config/m68k/m68k.c (m68k_conditional_register_usage): Likewise.
	* config/mips/mips.c (mips_class_max_nregs): Likewise.
	* config/pdp11/pdp11.c (pdp11_conditional_register_usage): Likewise.
	* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
	* config/sh/sh.c (output_stack_adjust): Likewise.
	* final.c (collect_fn_hard_reg_usage): Likewise.
	(get_call_reg_set_usage): Likewise.
	* ira-build.c (ira_create_object, remove_low_level_allocnos)
	(ira_flattening): Likewise.
	* ira-color.c (add_allocno_hard_regs, add_allocno_hard_regs_to_forest)
	(setup_left_conflict_sizes_p, setup_profitable_hard_regs)
	(get_conflict_and_start_profitable_regs, allocno_reload_assign)
	(ira_reassign_pseudos): Likewise.
	* ira-conflicts.c (print_allocno_conflicts): Likewise.
	(ira_build_conflicts): Likewise.
	* ira-costs.c (restrict_cost_classes): Likewise.
	(setup_regno_cost_classes_by_aclass): Likewise.
	* ira.c (setup_class_hard_regs, setup_alloc_regs): Likewise.
	(setup_reg_subclasses, setup_class_subset_and_memory_move_costs)
	(setup_stack_reg_pressure_class, setup_pressure_classes)
	(setup_allocno_and_important_classes, setup_class_translate_array)
	(setup_reg_class_relations, setup_prohibited_class_mode_regs)
	(ira_setup_eliminable_regset): Likewise.
	* lra-assigns.c (find_hard_regno_for_1): Likewise.
	(setup_live_pseudos_and_spill_after_risky_transforms): Likewise.
	* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
	(process_alt_operands, inherit_in_ebb): Likewise.
	* lra-lives.c (process_bb_lives): Likewise.
	* lra-spills.c (assign_spill_hard_regs): Likewise.
	* lra.c (lra): Likewise.
	* mode-switching.c (new_seginfo): Likewise.
	* postreload.c (reload_combine): Likewise.
	* reg-stack.c (straighten_stack): Likewise.
	* reginfo.c (save_register_info, restore_register_info): Likewise.
	(init_reg_sets_1, record_subregs_of_mode): Likewise
	* regrename.c (create_new_chain, rename_chains): Likewise.
	* reload1.c (order_regs_for_reload, find_reg): Likewise.
	(find_reload_regs): Likewise.
	* resource.c (find_dead_or_set_registers): Likewise.
	(mark_target_live_regs): Likewise.
	* sel-sched.c (mark_unavailable_hard_regs): Likewise.

From-SVN: r275528

1 files changed, 32 insertions, 38 deletions

diff --git a/gcc/ira.c b/gcc/ira.c
index 66f1fc1..a2ebbab 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -471,7 +471,7 @@ setup_class_hard_regs (void)
   ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     {
-      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+      temp_hard_regset = reg_class_contents[cl];
       AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
       CLEAR_HARD_REG_SET (processed_hard_reg_set);
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
@@ -514,7 +514,7 @@ setup_alloc_regs (bool use_hard_frame_p)
 #ifdef ADJUST_REG_ALLOC_ORDER
   ADJUST_REG_ALLOC_ORDER;
 #endif
-  COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_nonglobal_reg_set);
+  no_unit_alloc_regs = fixed_nonglobal_reg_set;
   if (! use_hard_frame_p)
     SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
   setup_class_hard_regs ();
@@ -541,7 +541,7 @@ setup_reg_subclasses (void)
       if (i == (int) NO_REGS)
 	continue;
 
-      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+      temp_hard_regset = reg_class_contents[i];
       AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
       if (hard_reg_set_empty_p (temp_hard_regset))
 	continue;
@@ -550,7 +550,7 @@ setup_reg_subclasses (void)
 	  {
 	    enum reg_class *p;
 
-	    COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
+	    temp_hard_regset2 = reg_class_contents[j];
 	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
 	    if (! hard_reg_set_subset_p (temp_hard_regset,
 					 temp_hard_regset2))
@@ -605,9 +605,9 @@ setup_class_subset_and_memory_move_costs (void)
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
       {
-	COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	temp_hard_regset = reg_class_contents[cl];
 	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+	temp_hard_regset2 = reg_class_contents[cl2];
 	AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
 	ira_class_subset_p[cl][cl2]
 	  = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
@@ -757,7 +757,7 @@ setup_stack_reg_pressure_class (void)
     for (i = 0; i < ira_pressure_classes_num; i++)
       {
 	cl = ira_pressure_classes[i];
-	COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset);
+	temp_hard_regset2 = temp_hard_regset;
 	AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
 	size = hard_reg_set_size (temp_hard_regset2);
 	if (best < size)
@@ -816,7 +816,7 @@ setup_pressure_classes (void)
 		 register pressure class.  */
 	      for (m = 0; m < NUM_MACHINE_MODES; m++)
 		{
-		  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+		  temp_hard_regset = reg_class_contents[cl];
 		  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 		  AND_COMPL_HARD_REG_SET (temp_hard_regset,
 					  ira_prohibited_class_mode_regs[cl][m]);
@@ -833,7 +833,7 @@ setup_pressure_classes (void)
 	    }
 	  curr = 0;
 	  insert_p = true;
-	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	  temp_hard_regset = reg_class_contents[cl];
 	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	  /* Remove so far added pressure classes which are subset of the
 	     current candidate class.  Prefer GENERAL_REGS as a pressure
@@ -845,7 +845,7 @@ setup_pressure_classes (void)
 	  for (i = 0; i < n; i++)
 	    {
 	      cl2 = pressure_classes[i];
-	      COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+	      temp_hard_regset2 = reg_class_contents[cl2];
 	      AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
 	      if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2)
 		  && (! hard_reg_set_equal_p (temp_hard_regset,
@@ -882,7 +882,7 @@ setup_pressure_classes (void)
        registers available for the allocation.  */
     CLEAR_HARD_REG_SET (temp_hard_regset);
     CLEAR_HARD_REG_SET (temp_hard_regset2);
-    COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs);
+    ignore_hard_regs = no_unit_alloc_regs;
     for (cl = 0; cl < LIM_REG_CLASSES; cl++)
       {
 	/* For some targets (like MIPS with MD_REGS), there are some
@@ -1001,12 +1001,12 @@ setup_allocno_and_important_classes (void)
      same set of hard registers.  */
   for (i = 0; i < LIM_REG_CLASSES; i++)
     {
-      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+      temp_hard_regset = reg_class_contents[i];
       AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
       for (j = 0; j < n; j++)
 	{
 	  cl = classes[j];
-	  COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+	  temp_hard_regset2 = reg_class_contents[cl];
 	  AND_COMPL_HARD_REG_SET (temp_hard_regset2,
 				  no_unit_alloc_regs);
 	  if (hard_reg_set_equal_p (temp_hard_regset,
@@ -1037,13 +1037,12 @@ setup_allocno_and_important_classes (void)
   for (cl = 0; cl < N_REG_CLASSES; cl++)
     if (ira_class_hard_regs_num[cl] > 0)
       {
-	COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+	temp_hard_regset = reg_class_contents[cl];
 	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	set_p = false;
 	for (j = 0; j < ira_allocno_classes_num; j++)
 	  {
-	    COPY_HARD_REG_SET (temp_hard_regset2,
-			       reg_class_contents[ira_allocno_classes[j]]);
+	    temp_hard_regset2 = reg_class_contents[ira_allocno_classes[j]];
 	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
 	    if ((enum reg_class) cl == ira_allocno_classes[j])
 	      break;
@@ -1118,8 +1117,7 @@ setup_class_translate_array (enum reg_class *class_translate,
       for (i = 0; i < classes_num; i++)
 	{
 	  aclass = classes[i];
-	  COPY_HARD_REG_SET (temp_hard_regset,
-			     reg_class_contents[aclass]);
+	  temp_hard_regset = reg_class_contents[aclass];
 	  AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
 	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	  if (! hard_reg_set_empty_p (temp_hard_regset))
@@ -1223,9 +1221,9 @@ setup_reg_class_relations (void)
 	  ira_reg_classes_intersect_p[cl1][cl2] = false;
 	  ira_reg_class_intersect[cl1][cl2] = NO_REGS;
 	  ira_reg_class_subset[cl1][cl2] = NO_REGS;
-	  COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
+	  temp_hard_regset = reg_class_contents[cl1];
 	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	  COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]);
+	  temp_set2 = reg_class_contents[cl2];
 	  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 	  if (hard_reg_set_empty_p (temp_hard_regset)
 	      && hard_reg_set_empty_p (temp_set2))
@@ -1264,15 +1262,15 @@ setup_reg_class_relations (void)
 	    }
 	  ira_reg_class_subunion[cl1][cl2] = NO_REGS;
 	  ira_reg_class_superunion[cl1][cl2] = NO_REGS;
-	  COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]);
+	  intersection_set = reg_class_contents[cl1];
 	  AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
 	  AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
-	  COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]);
+	  union_set = reg_class_contents[cl1];
 	  IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]);
 	  AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs);
 	  for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++)
 	    {
-	      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]);
+	      temp_hard_regset = reg_class_contents[cl3];
 	      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
 	      if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
 		{
@@ -1281,10 +1279,9 @@ setup_reg_class_relations (void)
 		     of CL1 and CL2.  */
 		  if (important_class_p[cl3])
 		    {
-		      COPY_HARD_REG_SET
-			(temp_set2,
-			 reg_class_contents
-			 [(int) ira_reg_class_intersect[cl1][cl2]]);
+		      temp_set2
+			= (reg_class_contents
+			   [ira_reg_class_intersect[cl1][cl2]]);
 		      AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 		      if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 			  /* If the allocatable hard register sets are
@@ -1302,9 +1299,8 @@ setup_reg_class_relations (void)
 					   ira_reg_class_intersect[cl1][cl2]])))))
 			ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
 		    }
-		  COPY_HARD_REG_SET
-		    (temp_set2,
-		     reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]);
+		  temp_set2
+		    = reg_class_contents[ira_reg_class_subset[cl1][cl2]];
 		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 		  if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 		      /* Ignore unavailable hard registers and prefer
@@ -1322,9 +1318,8 @@ setup_reg_class_relations (void)
 		  /* CL3 allocatable hard register set is inside of
 		     union of allocatable hard register sets of CL1
 		     and CL2.  */
-		  COPY_HARD_REG_SET
-		    (temp_set2,
-		     reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]);
+		  temp_set2
+		    = reg_class_contents[ira_reg_class_subunion[cl1][cl2]];
 		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 	 	  if (ira_reg_class_subunion[cl1][cl2] == NO_REGS
 		      || (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
@@ -1347,9 +1342,8 @@ setup_reg_class_relations (void)
 		  /* CL3 allocatable hard register set contains union
 		     of allocatable hard register sets of CL1 and
 		     CL2.  */
-		  COPY_HARD_REG_SET
-		    (temp_set2,
-		     reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]);
+		  temp_set2
+		    = reg_class_contents[ira_reg_class_superunion[cl1][cl2]];
 		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
 	 	  if (ira_reg_class_superunion[cl1][cl2] == NO_REGS
 		      || (hard_reg_set_subset_p (temp_hard_regset, temp_set2)
@@ -1499,7 +1493,7 @@ setup_prohibited_class_mode_regs (void)
 
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     {
-      COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+      temp_hard_regset = reg_class_contents[cl];
       AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
       for (j = 0; j < NUM_MACHINE_MODES; j++)
 	{
@@ -2305,7 +2299,7 @@ ira_setup_eliminable_regset (void)
   if (frame_pointer_needed)
     df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true);
     
-  COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs);
+  ira_no_alloc_regs = no_unit_alloc_regs;
   CLEAR_HARD_REG_SET (eliminable_regset);
 
   compute_regs_asm_clobbered ();