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| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-15 13:52:20 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-16 15:45:37 +0100 |
| commit | 26bebf576ddcdcfb596f07e8c2896f17c48516e7 (patch) | |
| tree | df9a410eb6390626a266647b79738e148bc82e3a /gcc/ipa-inline-transform.c | |
| parent | d7a65edb629a010f7ef907d457343abcb569fab7 (diff) | |
| download | gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.zip gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.tar.gz gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.tar.bz2 | |
aarch64: Fix mismatched SVE predicate modes [PR94606]
For this testcase we ended up generating the invalid rtl:
(insn 10 9 11 2 (set (reg:VNx16BI 105)
(and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
(reg:VNx16BI 104))
(reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
(nil))
Fixed by taking the VNx16BI lowpart. It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.
2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/94606
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
the VNx16BI lowpart of the recursively-generated constant.
gcc/testsuite/
PR target/94606
* gcc.dg/vect/pr94606.c: New test.
Diffstat (limited to 'gcc/ipa-inline-transform.c')
0 files changed, 0 insertions, 0 deletions