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| author | Kong Lingling <lingling.kong@intel.com> | 2023-03-23 14:34:36 +0800 |
|---|---|---|
| committer | Hongyu Wang <hongyu.wang@intel.com> | 2023-10-07 16:34:29 +0800 |
| commit | bc4466b94e91f4d2a051a9beba45187e7c23615c (patch) | |
| tree | 4e380e708626b2be7c411855590e7df0c02375b3 /gcc/graphite-optimize-isl.cc | |
| parent | 7866984ba427dc56a12ee1b8d99feb4927b834b1 (diff) | |
| download | gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.zip gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.tar.gz gcc-bc4466b94e91f4d2a051a9beba45187e7c23615c.tar.bz2 | |
[APX EGPR] middle-end: Add insn argument to base_reg_class
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add new macros with insn parameters to base_reg_class
for lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argument and new macro
INSN_BASE_REG_CLASS.
(regno_ok_for_base_p_1): Add insn argument and new macro
REGNO_OK_FOR_INSN_BASE_P.
(regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1.
* doc/tm.texi: Document INSN_BASE_REG_CLASS and
REGNO_OK_FOR_INSN_BASE_P.
* doc/tm.texi.in: Ditto.
* lra-constraints.cc (process_address_1): Pass insn to
base_reg_class.
(curr_insn_transform): Ditto.
* reload.cc (find_reloads): Ditto.
(find_reloads_address): Ditto.
(find_reloads_address_1): Ditto.
(find_reloads_subreg_address): Ditto.
* reload1.cc (maybe_fix_stack_asms): Ditto.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Diffstat (limited to 'gcc/graphite-optimize-isl.cc')
0 files changed, 0 insertions, 0 deletions