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| author | Kong Lingling <lingling.kong@intel.com> | 2023-03-24 14:06:48 +0800 |
|---|---|---|
| committer | Hongyu Wang <hongyu.wang@intel.com> | 2023-10-07 16:34:31 +0800 |
| commit | 797b89329606501dcd56919264b5b6e39ebc7b43 (patch) | |
| tree | 0818bd2e0bb464de6aef51097bb7a020655369d5 /gcc/graphite-optimize-isl.cc | |
| parent | e4e8b60a4fc99e2aa399518f121a8a3d9f888520 (diff) | |
| download | gcc-797b89329606501dcd56919264b5b6e39ebc7b43.zip gcc-797b89329606501dcd56919264b5b6e39ebc7b43.tar.gz gcc-797b89329606501dcd56919264b5b6e39ebc7b43.tar.bz2 | |
[APX EGPR] Handle legacy insns that only support GPR16 (2/5)
These legacy insns in opcode map2/3 have vex but no evex
counterpart, disable EGPR for them by adjusting alternatives and
attr_gpr32.
insn list:
1. phaddw/vphaddw, phaddd/vphaddd, phaddsw/vphaddsw
2. phsubw/vphsubw, phsubd/vphsubd, phsubsw/vphsubsw
3. psignb/vpsginb, psignw/vpsignw, psignd/vpsignd
4. blendps/vblendps, blendpd/vblendpd
5. blendvps/vblendvps, blendvpd/vblendvpd
6. pblendvb/vpblendvb, pblendw/vpblendw
7. mpsadbw/vmpsadbw
8. dpps/vddps, dppd/vdppd
9. pcmpeqq/vpcmpeqq, pcmpgtq/vpcmpgtq
gcc/ChangeLog:
* config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3): Set
attr gpr32 0 and constraint jm/ja to all mem alternatives.
(ssse3_ph<plusminus_mnemonic>wv8hi3): Likewise.
(ssse3_ph<plusminus_mnemonic>wv4hi3): Likewise.
(avx2_ph<plusminus_mnemonic>dv8si3): Likewise.
(ssse3_ph<plusminus_mnemonic>dv4si3): Likewise.
(ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
(<ssse3_avx2>_psign<mode>3): Likewise.
(ssse3_psign<mode>3): Likewise.
(<sse4_1>_blend<ssemodesuffix><avxsizesuffix): Likewise.
(<sse4_1>_blendv<ssemodesuffix><avxsizesuffix): Likewise.
(*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt): Likewise.
(*<sse4_1>_blendv<ssefltmodesuff)ix><avxsizesuffix>_not_ltint: Likewise.
(<sse4_1>_dp<ssemodesuffix><avxsizesuffix>): Likewise.
(<sse4_1_avx2>_mpsadbw): Likewise.
(<sse4_1_avx2>_pblendvb): Likewise.
(*<sse4_1_avx2>_pblendvb_lt): Likewise.
(sse4_1_pblend<ssemodesuffix>): Likewise.
(*avx2_pblend<ssemodesuffix>): Likewise.
(avx2_permv2ti): Likewise.
(*avx_vperm2f128<mode>_nozero): Likewise.
(*avx2_eq<mode>3): Likewise.
(*sse4_1_eqv2di3): Likewise.
(sse4_2_gtv2di3): Likewise.
(avx2_gt<mode>3): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-legacy-insn-check-norex2.c: Add
sse/vex intrinsic tests.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Diffstat (limited to 'gcc/graphite-optimize-isl.cc')
0 files changed, 0 insertions, 0 deletions