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| author | Kito Cheng <kito.cheng@sifive.com> | 2023-12-25 16:45:21 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-01-04 15:52:33 +0800 |
| commit | 73a4f67b9c8c497d87fda44160953293bc4e11e5 (patch) | |
| tree | ad51b61713d990a4e4b75d0e0b430fb2936cc9bd /gcc/go | |
| parent | 15053a3e168e112b9e1b0c9be4bba06cf5be964f (diff) | |
| download | gcc-73a4f67b9c8c497d87fda44160953293bc4e11e5.zip gcc-73a4f67b9c8c497d87fda44160953293bc4e11e5.tar.gz gcc-73a4f67b9c8c497d87fda44160953293bc4e11e5.tar.bz2 | |
RISC-V: Fix misaligned stack offset for interrupt function
`interrupt` function will backup fcsr register, but it fixed to SImode,
it's not big issue since fcsr only used 8 bits so far, however the
offset should still using UNITS_PER_WORD to prevent the stack offset
become non 8 byte aligned, it will cause problem for RV64.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
offset of fcsr.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/interrupt-misaligned.c: New.
Diffstat (limited to 'gcc/go')
0 files changed, 0 insertions, 0 deletions