RISC-V: Bugfix for the RVV const vector

This patch would like to fix one bug of const vector for interleave.
Assume we need to generate interleave const vector like below.

 V = {{4, -4, 3, -3, 2, -2, 1, -1,}

Before this patch:
vsetvl a3, zero, e64, m8, ta, ma
vid.v       v8            v8 =  {0, 1, 2, 3, 4}
li          a6, -1
vmul.vx     v8, v8, a6    v8 =  {-0, -1, -2, -3, -4}
vadd.vi     v24, v8, 4    v24 = { 4,  3,  2,  1,  0}
vadd.vi     v8, v8, -4    v8 =  {-4, -5, -6, -7, -8}
li          a6, 32
vsll.vx     v8, v8, a6    v8 =  {0, -4, 0, -5, 0, -6, 0, -7,} for e32
vor         v24, v24, v8  v24 = {4, -4, 3, -5, 2, -6, 1, -7,} for e32

After this patch:
vsetvli a6,zero,e64,m8,ta,ma
vid.v  v8                  v8 =  {0, 1, 2, 3, 4}
li a7,-1
vmul.vx v16,v8,a7         v16 = {-0, -1, -2, -3, -4}
vaddvi v16,v16,4          v16 = { 4,  3,  2,  1, 0}
vaddvi v8,v8,-4           v8 =  {-4, -3, -2, -1, 0}
li a7,32
vsll.vx v8,v8,a7          v8 =  {0, -4, 0, -3, 0, -2,} for e32
vor.vv v16,v16,v8         v8 =  {4, -4, 3, -3, 2, -2,} for e32

It is not easy to add asm check stable enough for this case, as we need
to check the vadd -4 target comes from the vid output, which crosses 4
instructions up to point. Thus there is no test here and will be covered
by gcc.dg/vect/pr92420.c in the underlying patches.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Take step2
	instead of step1 for second series.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions