Disparage slightly the mask register alternative for bitwise operations.

The avx512 supports bitwise operations with mask registers, but the
throughput of those instructions is much lower than that of the
corresponding gpr version, so we would additionally disparages
slightly the mask register alternative for bitwise operations in the
LRA.

Also when allocano cost of GENERAL_REGS is same as MASK_REGS, allocate
MASK_REGS first since it has already been disparaged.

gcc/ChangeLog:

	PR target/101142
	* config/i386/i386.md: (*anddi_1): Disparage slightly the mask
	register alternative.
	(*and<mode>_1): Ditto.
	(*andqi_1): Ditto.
	(*andn<mode>_1): Ditto.
	(*<code><mode>_1): Ditto.
	(*<code>qi_1): Ditto.
	(*one_cmpl<mode>2_1): Ditto.
	(*one_cmplsi2_1_zext): Ditto.
	(*one_cmplqi2_1): Ditto.
	* config/i386/i386.c (x86_order_regs_for_local_alloc): Change
	the order of mask registers to be before general registers.

gcc/testsuite/ChangeLog:

	PR target/101142
	* gcc.target/i386/spill_to_mask-1.c: Adjust testcase.
	* gcc.target/i386/spill_to_mask-2.c: Adjust testcase.
	* gcc.target/i386/spill_to_mask-3.c: Adjust testcase.
	* gcc.target/i386/spill_to_mask-4.c: Adjust testcase.

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