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author | Segher Boessenkool <segher@kernel.crashing.org> | 2017-11-07 20:33:57 +0100 |
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committer | Segher Boessenkool <segher@gcc.gnu.org> | 2017-11-07 20:33:57 +0100 |
commit | b15ef5d3f8a611af67254cdfaf126412872ca95c (patch) | |
tree | 267dcc501467af54d2c28993edcd7977a5214e4f /gcc/gimplify.c | |
parent | d4bc3829f139406a9b8d238d834fb1580f68e1ec (diff) | |
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rs6000: Use isel for the cstore patterns
We currently generate (sometimes pretty long) sequences of integer
insns to implement the various cstore patterns. If the CPU has a fast
isel, we can use that at the same latency as of just two integer insns
(you also get a load immediate of 1, and sometimes one of 0 as well,
but those are not in the critical path: they don't depend on any other
instruction).
There are a few patterns that already are implemented with just two
instructions; so don't use isel in that case (I still need to check
all lt/gt/ltu/gtu/le/leu/ge/geu patterns with all SI/DI combinations,
one or two might be better without isel).
This introduces a new GPR2 mode iterator, for those patterns that use
two independent integer modes.
* config/rs6000/rs6000.md (GPR2): New mode_iterator.
("cstore<mode>4"): Don't always expand with rs6000_emit_int_cmove for
eq and ne if TARGET_ISEL.
(cmp): New code_iterator.
(UNS, UNSU_, UNSIK): New code_attrs.
(<code><GPR:mode><GPR2:mode>2_isel): New define_insn_and_split.
("eq<mode>3"): New define_expand, rename the define_insn_and_split
to...
("eq<mode>3"): ... this.
("ne<mode>3"): New define_expand, rename the define_insn_and_split
to...
("ne<mode>3"): ... this.
From-SVN: r254508
Diffstat (limited to 'gcc/gimplify.c')
0 files changed, 0 insertions, 0 deletions