RISC-V: Add RVV comparison autovectorization

This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.

The testcases are leveraged from Richard. So include Richard as co-author.

And this patch is the prerequisite patch for my current middle-end work.
Without this patch, I can't support len_mask_xxx middle-end pattern
since the mask is generated by comparison.

For example,
for (int i...; i < n.)
  if (cond[i])
     a[i] = b[i]

We need len_mask_load/len_mask_store for such code and I am gonna
support them in the middle-end after this patch is merged.

Both integer && floating (order and unorder) are tested.
built && regression passed.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>

gcc/ChangeLog:

	* config/riscv/autovec.md (@vcond_mask_<mode><vm>): New pattern.
	(vec_cmp<mode><vm>): New pattern.
	(vec_cmpu<mode><vm>): New pattern.
	(vcond<V:mode><VI:mode>): New pattern.
	(vcondu<V:mode><VI:mode>): New pattern.
	* config/riscv/riscv-protos.h (enum insn_type): Add new enum.
	(emit_vlmax_merge_insn): New function.
	(emit_vlmax_cmp_insn): Ditto.
	(emit_vlmax_cmp_mu_insn): Ditto.
	(expand_vec_cmp): Ditto.
	(expand_vec_cmp_float): Ditto.
	(expand_vcond): Ditto.
	* config/riscv/riscv-v.cc (emit_vlmax_merge_insn): Ditto.
	(emit_vlmax_cmp_insn): Ditto.
	(emit_vlmax_cmp_mu_insn): Ditto.
	(get_cmp_insn_code): Ditto.
	(expand_vec_cmp): Ditto.
	(expand_vec_cmp_float): Ditto.
	(expand_vcond): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp:
	* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: New test.

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