RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t

This patch support the RVV VREINTERPRET from the vbool*_t to the
vint*m1_t.  Aka:

vint*m1_t __riscv_vreinterpret_x_x(vbool*_t);

These APIs help the users to convert vector the vbool*_t to the LMUL=1
signed integer vint*_t.  According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#reinterpret-vbool-o-vintm1

For example, given below code.
vint8m1_t test_vreinterpret_v_b1_vint8m1 (vbool1_t src) {
  return __riscv_vreinterpret_v_b1_i8m1 (src);
}

It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v   v1,0(a1)
vs1r.v  v1,0(a0)
ret

Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
The reinterpret from vbool*_t to vuint*m1_t with lmul=1 will be coverred
in another PATCH.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
	for the eew size list.
	(LMUL1_LOG2): New macro for the log2 value of lmul=1.
	(main): Add signed_eew*_lmul1_interpret for indexer.
	* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
	Register vint*m1_t interpret function.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
	New macro for vint8m1_t.
	(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
	(vbool1_t): Add to signed_eew*_interpret_ops.
	(vbool2_t): Likewise.
	(vbool4_t): Likewise.
	(vbool8_t): Likewise.
	(vbool16_t): Likewise.
	(vbool32_t): Likewise.
	(vbool64_t): Likewise.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
	New macro for vint*m1_t.
	(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
	(required_extensions_p): Add vint8m1_t interpret case.
	* config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
	Add vint*m1_t interpret to base type.
	(signed_eew16_lmul1_interpret): Likewise.
	(signed_eew32_lmul1_interpret): Likewise.
	(signed_eew64_lmul1_interpret): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
	Enrich the test cases.

0 files changed, 0 insertions, 0 deletions