RISC-V: Add binary vx C/C++ support

gcc/ChangeLog:

	* config/riscv/constraints.md (Wdm): Adjust constraint.
	(Wbr): New constraint.
	* config/riscv/predicates.md (reg_or_int_operand): New predicate.
	* config/riscv/riscv-protos.h (emit_pred_op): Remove function.
	(emit_vlmax_op): New function.
	(emit_nonvlmax_op): Ditto.
	(simm32_p): Ditto.
	(neg_simm5_p): Ditto.
	(has_vi_variant_p): Ditto.
	* config/riscv/riscv-v.cc (emit_pred_op): Adjust function.
	(emit_vlmax_op): New function.
	(emit_nonvlmax_op): Ditto.
	(expand_const_vector): Adjust function.
	(legitimize_move): Ditto.
	(simm32_p): New function.
	(simm5_p): Ditto.
	(neg_simm5_p): Ditto.
	(has_vi_variant_p): Ditto.
	* config/riscv/riscv-vector-builtins-bases.cc (class vrsub): New class.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (vmin): Remove
	unsigned cases.
	(vmax): Ditto.
	(vminu): Remove signed cases.
	(vmaxu): Ditto.
	(vdiv): Remove unsigned cases.
	(vrem): Ditto.
	(vdivu): Remove signed cases.
	(vremu): Ditto.
	(vadd): Adjust.
	(vsub): Ditto.
	(vrsub): New class.
	(vand): Adjust.
	(vor): Ditto.
	(vxor): Ditto.
	(vmul): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_U_OPS): New macro.
	* config/riscv/riscv.h: change VL/VTYPE as fixed reg.
	* config/riscv/vector-iterators.md: New iterators.
	* config/riscv/vector.md (@pred_broadcast<mode>): Adjust pattern for vx
	support.
	(@pred_<optab><mode>_scalar): New pattern.
	(@pred_sub<mode>_reverse_scalar): Ditto.
	(*pred_<optab><mode>_scalar): Ditto.
	(*pred_<optab><mode>_extended_scalar): Ditto.
	(*pred_sub<mode>_reverse_scalar): Ditto.
	(*pred_sub<mode>_extended_reverse_scalar): Ditto.

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