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| author | Pan Li <pan2.li@intel.com> | 2023-11-13 11:06:38 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-13 11:13:06 +0800 |
| commit | 401dc18184af6b32a3ccbe1eaeed0c7ff9ae1d5a (patch) | |
| tree | 3d853863eae7b26ed38ecdc6650c966282473d72 /gcc/gimple-range-cache.cc | |
| parent | 5dfa501d2f2e58f2448466c75d6dbebce669638f (diff) | |
| download | gcc-401dc18184af6b32a3ccbe1eaeed0c7ff9ae1d5a.zip gcc-401dc18184af6b32a3ccbe1eaeed0c7ff9ae1d5a.tar.gz gcc-401dc18184af6b32a3ccbe1eaeed0c7ff9ae1d5a.tar.bz2 | |
RISC-V: Fix RVV dynamic frm tests failure
The hancement of mode-switching performs some optimization when
emit the frm backup insn, some redudant fsrm insns are removed
for the following test cases.
This patch would like to adjust the asm check for above optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: Adjust
the asm checker.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/gimple-range-cache.cc')
0 files changed, 0 insertions, 0 deletions