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| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:56 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:34:47 +0800 |
| commit | 773110dea48baed989f2b92bf2e1689cc2d87b60 (patch) | |
| tree | 83dc483deb8afaf748360e1636a8909fccd3b179 /gcc/gimple-loop-versioning.cc | |
| parent | 95c6fb6a841989c47213fedca689de1d50658ecf (diff) | |
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MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2
The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
for ISA_HAS_MIPS16E2.
(ISA_HAS_SYNC): Same as above.
(ISA_HAS_LL_SC): Same as above.
Diffstat (limited to 'gcc/gimple-loop-versioning.cc')
0 files changed, 0 insertions, 0 deletions