RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

When the source mode is potentially larger than one vector (e.g. an
LMUL2 mode for VLEN=128) we don't know which vector the subreg actually
refers to.  For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI))
could actually be the a full (high) vector register of a two-register
group (at VLEN=128) or the higher part of a single register (at VLEN>128).

As the subreg is statically ambiguous we prevent such situations in
can_change_mode_class.

The culprit in PR116086 is

 _12 = BIT_FIELD_REF <vect_cst__42, 128, 128>;

which can be expanded with a vector-vector extract (from V4DI to V2DI).
This patch adds a VLS-mode vector-vector extract that handles "halving"
cases like this one by sliding down the source vector, thus making sure
the correct part is used.

	PR target/116086

gcc/ChangeLog:

	* config/riscv/autovec.md (vec_extract<mode><v_half>): Add
	vector-vector extract for VLS modes.
	* config/riscv/riscv.cc (riscv_can_change_mode_class): Forbid
	VLS modes larger than one vector.
	* config/riscv/vector-iterators.md: Add vector-vector extract
	iterators.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add effective target checks for
	zvl256b and zvl512b.
	* gcc.target/riscv/rvv/autovec/pr116086-2-run.c: New test.
	* gcc.target/riscv/rvv/autovec/pr116086-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr116086.c: New test.

0 files changed, 0 insertions, 0 deletions