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| author | xuli <xuli1@eswincomputing.com> | 2023-09-21 03:04:56 +0000 |
|---|---|---|
| committer | xuli <xuli1@eswincomputing.com> | 2023-09-21 04:00:06 +0000 |
| commit | 47065ff360292c683670efb96df4b61f57dc1d9a (patch) | |
| tree | 844ad15895cd94362051c5ad0749870206997097 /gcc/gimple-loop-interchange.cc | |
| parent | 4e35cf2ea1fbcdf798b37b2e00d9977683b17b8a (diff) | |
| download | gcc-47065ff360292c683670efb96df4b61f57dc1d9a.zip gcc-47065ff360292c683670efb96df4b61f57dc1d9a.tar.gz gcc-47065ff360292c683670efb96df4b61f57dc1d9a.tar.bz2 | |
RISC-V: Optimized for strided load/store with stride == element width[PR111450]
When stride == element width, vlsse should be optimized into vle.v.
vsse should be optimized into vse.v.
PR target/111450
gcc/ChangeLog:
* config/riscv/constraints.md (c01): const_int 1.
(c02): const_int 2.
(c04): const_int 4.
(c08): const_int 8.
* config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand.
(vector_eew16_stride_operand): Ditto.
(vector_eew32_stride_operand): Ditto.
(vector_eew64_stride_operand): Ditto.
* config/riscv/vector-iterators.md: New iterator for stride operand.
* config/riscv/vector.md: Add stride = element width constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr111450.c: New test.
Diffstat (limited to 'gcc/gimple-loop-interchange.cc')
0 files changed, 0 insertions, 0 deletions