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author | Pan Li <pan2.li@intel.com> | 2023-05-11 18:50:56 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-05-11 19:06:44 +0800 |
commit | 0918360d709a32294913aef4392cec6c1dec1857 (patch) | |
tree | 8dfac10cd9d51ba431cc46965f928ae980158801 /gcc/gimple-loop-interchange.cc | |
parent | 0440b774ea3311d65027aa7b1d26b62b7d8538ea (diff) | |
download | gcc-0918360d709a32294913aef4392cec6c1dec1857.zip gcc-0918360d709a32294913aef4392cec6c1dec1857.tar.gz gcc-0918360d709a32294913aef4392cec6c1dec1857.tar.bz2 |
VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV
This patch is going to be commited after bootstrap && regression on X86
PASSED.
Thanks Richards.
gcc/ChangeLog:
* cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
* gimple-loop-interchange.cc
(tree_loop_interchange::map_inductions_to_loop): Ditto.
* tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto.
* tree-ssa-loop-ivopts.cc (create_new_iv): Ditto.
* tree-ssa-loop-manip.cc (create_iv): Ditto.
(tree_transform_and_unroll_loop): Ditto.
(canonicalize_loop_ivs): Ditto.
* tree-ssa-loop-manip.h (create_iv): Ditto.
* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto.
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
Ditto.
(vect_set_loop_condition_normal): Ditto.
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto.
* tree-vect-stmts.cc (vectorizable_store): Ditto.
(vectorizable_load): Ditto.
Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
Diffstat (limited to 'gcc/gimple-loop-interchange.cc')
-rw-r--r-- | gcc/gimple-loop-interchange.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/gimple-loop-interchange.cc b/gcc/gimple-loop-interchange.cc index 1b77bfd..e559037 100644 --- a/gcc/gimple-loop-interchange.cc +++ b/gcc/gimple-loop-interchange.cc @@ -1185,7 +1185,7 @@ tree_loop_interchange::map_inductions_to_loop (loop_cand &src, loop_cand &tgt) tree var_before, var_after; tree base = unshare_expr (iv->init_expr); tree step = unshare_expr (iv->step); - create_iv (base, step, SSA_NAME_VAR (iv->var), + create_iv (base, PLUS_EXPR, step, SSA_NAME_VAR (iv->var), tgt.m_loop, &incr_pos, false, &var_before, &var_after); bitmap_set_bit (m_dce_seeds, SSA_NAME_VERSION (var_before)); bitmap_set_bit (m_dce_seeds, SSA_NAME_VERSION (var_after)); |