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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2021-03-08 15:05:21 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2021-03-08 15:05:21 +0000 |
| commit | 0d9a70ea3881c284b7689b691d54d047b55b486d (patch) | |
| tree | ddc84555a643c6880d9a59687a1f70b22655a147 /gcc/gimple-array-bounds.cc | |
| parent | 81fee438512460f1be50d91ee5de452f8fe5cc18 (diff) | |
| download | gcc-0d9a70ea3881c284b7689b691d54d047b55b486d.zip gcc-0d9a70ea3881c284b7689b691d54d047b55b486d.tar.gz gcc-0d9a70ea3881c284b7689b691d54d047b55b486d.tar.bz2 | |
aarch64: Fix PR99437 - tighten shift predicates for narrowing shift patterns
In this bug combine forms the (R)SHRN(2) instructions with an invalid shift amount.
The intrinsic expanders for these patterns validate the right shift amount but if the
final patterns end up being matched by combine (or other RTL passes I suppose) they
still let the wrong const_vector through.
This patch tightens up the predicates for the instructions involved by using predicates
for the right shift amount const_vectors.
gcc/ChangeLog:
PR target/99437
* config/aarch64/predicates.md (aarch64_simd_shift_imm_vec_qi): Define.
(aarch64_simd_shift_imm_vec_hi): Likewise.
(aarch64_simd_shift_imm_vec_si): Likewise.
(aarch64_simd_shift_imm_vec_di): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le): Use
predicate from above.
(aarch64_shrn<mode>_insn_be): Likewise.
(aarch64_rshrn<mode>_insn_le): Likewise.
(aarch64_rshrn<mode>_insn_be): Likewise.
(aarch64_shrn2<mode>_insn_le): Likewise.
(aarch64_shrn2<mode>_insn_be): Likewise.
(aarch64_rshrn2<mode>_insn_le): Likewise.
(aarch64_rshrn2<mode>_insn_be): Likewise.
gcc/testsuite/ChangeLog:
PR target/99437
* gcc.target/aarch64/simd/pr99437.c: New test.
Diffstat (limited to 'gcc/gimple-array-bounds.cc')
0 files changed, 0 insertions, 0 deletions