RISC-V: Refactor vector reduction patterns

This patch adjust reduction patterns struct, change it from:
           (any_reduc:VI
             (vec_duplicate:VI
               (vec_select:<VEL>
                 (match_operand:<V_LMUL1> 4 "register_operand"      "   vr,   vr")
                 (parallel [(const_int 0)])))
             (match_operand:VI           3 "register_operand"      "   vr,   vr"))
to:
           (unspec:<V_LMUL1> [
             (match_operand:VI            3 "register_operand"      "   vr,   vr")
             (match_operand:<V_LMUL1>     4 "register_operand"      "   vr,   vr")
           ] ANY_REDUC)

The reason for the change is that the semantics of the previous pattern is incorrect.
GCC does not have a standard rtx code to express the reduction calculation process.
It makes more sense to use UNSPEC.

Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)),
so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop
and widen_freducop are redundant.

gcc/ChangeLog:

	* config/riscv/autovec.md: Change rtx code to unspec.
	* config/riscv/riscv-protos.h (expand_reduction): Change prototype.
	* config/riscv/riscv-v.cc (expand_reduction): Change prototype.
	* config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
	Removed.
	(class widen_freducop): Removed.
	* config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
	* config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
	(@pred_<reduc_op><mode>): New name.
	(@pred_widen_reduc_plus<v_su><mode>): Change name.
	(@pred_reduc_plus<order><mode>): Change name.
	(@pred_widen_reduc_plus<order><mode>): Change name.

0 files changed, 0 insertions, 0 deletions