diff options
| author | Wilco Dijkstra <wdijkstr@arm.com> | 2022-10-13 14:41:55 +0100 |
|---|---|---|
| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2022-10-13 14:56:27 +0100 |
| commit | 1cccf644ff92ac1145abdbf255d1862dd787875b (patch) | |
| tree | df0964bab5f5bc68c4e47db512b8fd4b9f038ca3 /gcc/genmodes.cc | |
| parent | 5cbaf84c191b9a3e3cb26545c808d208bdbf2ab5 (diff) | |
| download | gcc-1cccf644ff92ac1145abdbf255d1862dd787875b.zip gcc-1cccf644ff92ac1145abdbf255d1862dd787875b.tar.gz gcc-1cccf644ff92ac1145abdbf255d1862dd787875b.tar.bz2 | |
[AArch64] Improve bit tests [PR105773]
Since AArch64 sets all flags on logical operations, comparisons with zero
can be combined into an AND even if the condition is LE or GT. Add a new
CC_NZV mode used by ANDS/BICS/TST instructions.
gcc/
PR target/105773
* config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow
GT/LE for merging compare with zero into AND.
(aarch64_get_condition_code_1): Add CC_NZVmode support.
* config/aarch64/aarch64-modes.def: Add CC_NZV.
* config/aarch64/aarch64.md: Use CC_NZV in cmp+and patterns.
gcc/testsuite/
PR target/105773
* gcc.target/aarch64/ands_2.c: Test for ANDS.
* gcc.target/aarch64/bics_2.c: Test for BICS.
* gcc.target/aarch64/tst_2.c: Test for TST.
* gcc.target/aarch64/tst_imm_split_1.c: Fix test.
Diffstat (limited to 'gcc/genmodes.cc')
0 files changed, 0 insertions, 0 deletions