aarch64: Leveraging the use of STP instruction for vec_duplicate

The backend pattern for storing a pair of identical values in 32 and
64-bit modes with the machine instruction STP was missing, and
multiple instructions were needed to reproduce this behavior as a
result of failed RTL pattern match in combine pass.

For the test case:

typedef long long v2di __attribute__((vector_size (16)));
typedef int v2si __attribute__((vector_size (8)));

void
foo (v2di *x, long long a)
{
  v2di tmp = {a, a};
  *x = tmp;
}

void
foo2 (v2si *x, int a)
{
  v2si tmp = {a, a};
  *x = tmp;
}

at -O2 on aarch64 gives:

foo:
    stp x1, x1, [x0]
    ret
foo2:
    stp w1, w1, [x0]
    ret

instead of:

foo:
        dup     v0.2d, x1
        str     q0, [x0]
        ret
foo2:
        dup     v0.2s, w1
        str     d0, [x0]
        ret

Bootstrapped and regtested on aarch64-none-linux-gnu.

gcc/
	* config/aarch64/aarch64-simd.md(aarch64_simd_stp<mode>): New.
	* config/aarch64/constraints.md: Make "Umn" relaxed memory
	constraint.
	* config/aarch64/iterators.md(ldpstp_vel_sz): New.

gcc/testsuite/
	* gcc.target/aarch64/stp_vec_dup_32_64-1.c: New.

0 files changed, 0 insertions, 0 deletions