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| author | Jin Ma <jinma@linux.alibaba.com> | 2024-09-07 10:29:02 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-07 10:30:24 -0600 |
| commit | d620499b3a24f14cfb98529640584e63d7eca149 (patch) | |
| tree | 61594917f3fae3f97469bfb783b75e5150663db4 /gcc/gcov.cc | |
| parent | 113a6da9bf91c52b026dddfc51144f9124fd803b (diff) | |
| download | gcc-d620499b3a24f14cfb98529640584e63d7eca149.zip gcc-d620499b3a24f14cfb98529640584e63d7eca149.tar.gz gcc-d620499b3a24f14cfb98529640584e63d7eca149.tar.bz2 | |
[PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector
Since the THeadVector vsetvli does not support vl as an immediate, we
need to convert 0 to zero when outputting asm.
PR target/116592
gcc/ChangeLog:
* config/riscv/thead.cc (th_asm_output_opcode): Change '0' to
"zero"
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test.
Diffstat (limited to 'gcc/gcov.cc')
0 files changed, 0 insertions, 0 deletions