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| author | Tejas Belagod <tbelagod@arm.com> | 2021-08-09 11:33:30 +0100 |
|---|---|---|
| committer | Tejas Belagod <tbelagod@arm.com> | 2021-08-09 12:54:14 +0100 |
| commit | e2e0b85c1e7cb53fd720df0d09278e3d485c733e (patch) | |
| tree | be000387417201afd4780cbbc54c1e41d2c7adc9 /gcc/gcov-counter.def | |
| parent | 0095afa82a34cdf59a40112b621b348e0087ddb8 (diff) | |
| download | gcc-e2e0b85c1e7cb53fd720df0d09278e3d485c733e.zip gcc-e2e0b85c1e7cb53fd720df0d09278e3d485c733e.tar.gz gcc-e2e0b85c1e7cb53fd720df0d09278e3d485c733e.tar.bz2 | |
PR101609: Use the correct iterator for AArch64 vector right shift pattern
Loops containing long long shifts fail to vectorize due to the vectorizer
not being able to recognize long long right shifts. This is due to a bug
in the iterator used for the vashr and vlshr patterns in aarch64-simd.md.
2021-08-09 Tejas Belagod <tejas.belagod@arm.com>
gcc/ChangeLog
PR target/101609
* config/aarch64/aarch64-simd.md (vlshr<mode>3, vashr<mode>3): Use
the right iterator.
gcc/testsuite/ChangeLog
* gcc.target/aarch64/vect-shr-reg.c: New testcase.
* gcc.target/aarch64/vect-shr-reg-run.c: Likewise.
Diffstat (limited to 'gcc/gcov-counter.def')
0 files changed, 0 insertions, 0 deletions