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authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>2022-11-29 09:22:01 +0800
committerKito Cheng <kito.cheng@sifive.com>2022-12-02 00:14:22 +0800
commitc126e144d407bdc36c4204ab1b76b584b6514786 (patch)
tree2827bb714a452e5ec6de5a53c6bbed4e838dbb71 /gcc/gcc.cc
parent3b16afeb3f6aacf64b9f9c50b7cb9805a9dfff63 (diff)
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RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
1. vector.md: remove tail && mask policy operand for mask mode operations since we don't need them according to RVV ISA. 2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV modes including vector integer mode && vector float mode && vector bool mode are all use emit_pred_op function. For vector integer mode && vector float mode, we have instruction like vle.v/vse.v that we need tail && mask policy. However, for vector bool mode, the instruction is vlm/vsm that we don't need tail && mask policy. So we add a condition here to add tail && mask policy operand during expand if it is not a vector bool modes. This patch is to cleanup the code and make it be consistent with RVV ISA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov.
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