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| author | YunQiang Su <yunqiang.su@cipunited.com> | 2022-01-26 03:21:20 +0000 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2022-04-01 06:57:27 +0000 |
| commit | 15d683d4f0b390b27c54a7c92c6e4f33195bdc93 (patch) | |
| tree | 9ac8b550bd66fc6651da055da80da9f6a0a0ffe2 /gcc/function.cc | |
| parent | 5901a10bdf7a872697894f2e0990bff8b2e48c39 (diff) | |
| download | gcc-15d683d4f0b390b27c54a7c92c6e4f33195bdc93.zip gcc-15d683d4f0b390b27c54a7c92c6e4f33195bdc93.tar.gz gcc-15d683d4f0b390b27c54a7c92c6e4f33195bdc93.tar.bz2 | |
MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU
If MIPS MCU extension is enable, the IPL section in Cause and Status
registers has been expand to 8bit instead of 6bit.
In Cause: the bits are 10-17.
In Status: the bits are 10-16 and 18.
MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.
gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_prologue):
IPL is 8bit for MCU ASE.
Diffstat (limited to 'gcc/function.cc')
0 files changed, 0 insertions, 0 deletions