riscv: thead: Add support for the XTheadCondMov ISA extensions

This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding mov<mode>cc accordingly and adjust the cost
model.

gcc/ChangeLog:

	* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
	* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
	Add prototype.
	* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
	XTheadCondMov.
	(riscv_expand_conditional_move): New function.
	(riscv_expand_conditional_move_onesided): New function.
	* config/riscv/riscv.md: Add support for XTheadCondMov.
	* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
	support for XTheadCondMov.
	(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

0 files changed, 0 insertions, 0 deletions