RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.

The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
potential risks:

When the architecture adds pre-processing to `define_insn "adddi3"`, such as
`define_expend "adddi3"`, the gen_expand will be automatically called here,
causing the patern to emit directly, which will cause insn to enter REG_NOTE
for `DWARF` instead of patern.

The following error REG_NOTE occurred:
error: invalid rtl sharing found in the insn:
(insn 19 3 20 2 (parallel [
        ...
        ])
    (expr_list:REG_CFA_ADJUST_CFA
        (insn 18 0 0 (set (reg/f:DI 2 sp)
            (plus:DI (reg/f:DI 2 sp)
                (const_int -16 [0xfffffffffffffff0]))) -1
        (nil))))

In fact, the correct one should be the following:
(insn 19 3 20 2 (parallel [
        ...
        ])
    (expr_list:REG_CFA_ADJUST_CFA
        (set (reg/f:DI 2 sp)
            (plus:DI (reg/f:DI 2 sp)
                (const_int -16 [0xfffffffffffffff0])))))

Following the treatment of arm or other architectures, it is more reasonable to
use gen_SET here.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change
	gen_add3_insn to gen_rtx_SET.
	(riscv_adjust_libcall_cfi_epilogue): Likewise.

0 files changed, 0 insertions, 0 deletions