RISC-V: Early expand DImode vec_duplicate in RV32 system

An ICE was discovered in recent rounding autovec support:

config/riscv/riscv-v.cc:4314
   65 | }
      | ^
0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**,
rtx_def*, bool)
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-v.cc:4314
0x1fb1aa2 pre_vsetvl::remove_avl_operand()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3342
0x1fb18c1 pre_vsetvl::cleaup()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3308
0x1fb216d pass_vsetvl::lazy_vsetvl()
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3480
0x1fb2214 pass_vsetvl::execute(function*)
        /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3504

The root cause is that the RA reload into (set (reg) vec_duplicate:DI). However, it is not valid in RV32 system
since we don't have a single broadcast instruction DI scalar in RV32 system.
We should expand it early for RV32 system.

gcc/ChangeLog:

	* config/riscv/predicates.md: Adapt predicate.
	* config/riscv/riscv-protos.h (can_be_broadcasted_p): New function.
	* config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto.
	* config/riscv/vector.md (vec_duplicate<mode>): New pattern.
	(*vec_duplicate<mode>): Adapt vec_duplicate insn pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/sew64-rv32.c: New test.

0 files changed, 0 insertions, 0 deletions