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author | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-04-11 19:37:48 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2023-04-11 22:02:41 +0800 |
commit | 40fc8e3d4f600d89e6b065d6f12db7a816269c8f (patch) | |
tree | 0159b34bd41711e3c0d27754bbe279288b7a2cd2 /gcc/fortran | |
parent | b8e32978e3d9e3b88cd4f441edfdebfa395a5c26 (diff) | |
download | gcc-40fc8e3d4f600d89e6b065d6f12db7a816269c8f.zip gcc-40fc8e3d4f600d89e6b065d6f12db7a816269c8f.tar.gz gcc-40fc8e3d4f600d89e6b065d6f12db7a816269c8f.tar.bz2 |
RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104]
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
gcc/ChangeLog:
PR target/109104
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
(emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
* config/riscv/riscv.cc (vector_zero_call_used_regs): New.
(riscv_zero_call_used_regs): New.
(TARGET_ZERO_CALL_USED_REGS): New.
gcc/testsuite/ChangeLog:
PR target/109104
* gcc.target/riscv/zero-scratch-regs-1.c: New test.
* gcc.target/riscv/zero-scratch-regs-2.c: New test.
* gcc.target/riscv/zero-scratch-regs-3.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'gcc/fortran')
0 files changed, 0 insertions, 0 deletions