RISC-V: Split VF iterators for Zvfh(min).

When working on FP widening/narrowing I realized the Zvfhmin handling
is not ideal right now:  We use the "enabled" insn attribute to disable
instructions not available with Zvfhmin but only with Zvfh.

However, "enabled == 0" only disables insn alternatives, in our case all
of them when the mode is a HFmode.  The insn itself remains available
(e.g. for combine to match) and we end up with an insn without alternatives
that reload cannot handle --> ICE.

The proper solution is to disable the instruction for the respective
mode altogether.  This patch achieves this by splitting the VF as well
as VWEXTF iterators into variants with TARGET_ZVFH and
TARGET_VECTOR_ELEN_FP_16 (which is true when either TARGET_ZVFH or
TARGET_ZVFHMIN are true).  Also, VWCONVERTI, VHF and VHF_LMUL1 need
adjustments.

gcc/ChangeLog:

	* config/riscv/autovec.md: VF_AUTO -> VF.
	* config/riscv/vector-iterators.md: Introduce VF_ZVFHMIN,
	VWEXTF_ZVFHMIN and use TARGET_ZVFH in VWCONVERTI, VHF and
	VHF_LMUL1.
	* config/riscv/vector.md: Use new iterators.

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