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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-01-20 17:33:09 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-01-27 17:59:08 +0800 |
| commit | 0f024ff988aeaacd8d0f967c5f841ab20fb40c19 (patch) | |
| tree | a951342912671194d655a179b2e166433853bee1 /gcc/fortran/trans-openmp.cc | |
| parent | b0241ce6e37031e1cbde73d5389ec7f1d063e099 (diff) | |
| download | gcc-0f024ff988aeaacd8d0f967c5f841ab20fb40c19.zip gcc-0f024ff988aeaacd8d0f967c5f841ab20fb40c19.tar.gz gcc-0f024ff988aeaacd8d0f967c5f841ab20fb40c19.tar.bz2 | |
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
Diffstat (limited to 'gcc/fortran/trans-openmp.cc')
0 files changed, 0 insertions, 0 deletions