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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2022-07-15 15:25:53 +0100 |
|---|---|---|
| committer | Andrew Carlotti <andrew.carlotti@arm.com> | 2022-07-15 15:30:29 +0100 |
| commit | 5ba864c5d11a1c20891a1e054cb7814ec23de5c9 (patch) | |
| tree | e893e62dd87a50b92f28a8794ff6da631bc0e58f /gcc/fortran/trans-decl.cc | |
| parent | 23dd41c480fa9f06c33c1e6090bbae53869f85af (diff) | |
| download | gcc-5ba864c5d11a1c20891a1e054cb7814ec23de5c9.zip gcc-5ba864c5d11a1c20891a1e054cb7814ec23de5c9.tar.gz gcc-5ba864c5d11a1c20891a1e054cb7814ec23de5c9.tar.bz2 | |
aarch64: Add V1DI mode
We already have a V1DF mode, so this makes the vector modes more consistent.
Additionally, this allows us to recognise uint64x1_t and int64x1_t types given
only the mode and type qualifiers (e.g. in aarch64_lookup_simd_builtin_type).
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc
(v1di_UP): Add V1DI mode to _UP macros.
* config/aarch64/aarch64-modes.def (VECTOR_MODE): Add V1DI mode.
* config/aarch64/aarch64-simd-builtin-types.def: Use V1DI mode.
* config/aarch64/aarch64-simd.md
(vec_extractv2dfv1df): Replace with...
(vec_extract<mode><V1half>): ...this.
* config/aarch64/aarch64.cc
(aarch64_classify_vector_mode): Add V1DI mode.
* config/aarch64/iterators.md
(VQ_2E, V1HALF, V1half): New.
(nunits): Add V1DI mode.
Diffstat (limited to 'gcc/fortran/trans-decl.cc')
0 files changed, 0 insertions, 0 deletions