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| author | Eric Botcazou <ebotcazou@adacore.com> | 2021-03-12 17:07:20 +0100 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@adacore.com> | 2021-03-12 18:52:07 +0100 |
| commit | d8b84e2771fc2495493d0c66c3cba714484757d7 (patch) | |
| tree | 5f1bd91bcea4c1afdc7e6e4b07338429107de081 /gcc/fortran/trans-array.c | |
| parent | d0655763483008a421608d059cf26c93077621a9 (diff) | |
| download | gcc-d8b84e2771fc2495493d0c66c3cba714484757d7.zip gcc-d8b84e2771fc2495493d0c66c3cba714484757d7.tar.gz gcc-d8b84e2771fc2495493d0c66c3cba714484757d7.tar.bz2 | |
Fix memory constraint bug in SPARC back-end
It's a bug exposed by the recent LRA changes, whereby the T constraint
fails to behave properly when LRA is enabled (unlike when reload is
enabled). The patch also gets rid of the awkward W constraint, which
is strictly equivalent to m in 64-bit mode and, as a result, renames
the w constraint into W.
gcc/
PR target/99422
* config/sparc/constraints.md (w): Rename to...
(W): ... this and ditch previous implementation.
* config/sparc/sparc.md (*movdi_insn_sp64): Replace W with m.
(*movdf_insn_sp64): Likewise.
(*mov<VM64:mode>_insn_sp64): Likewise.
* config/sparc/sync.md (*atomic_compare_and_swap<mode>_1): Replace
w with W.
(atomic_compare_and_swap_leon3_1): Likewise.
(*atomic_compare_and_swapdi_v8plus): Likewise.
* config/sparc/sparc.c (memory_ok_for_ldd): Remove useless test on
architecture and add missing address validity check during LRA.
Diffstat (limited to 'gcc/fortran/trans-array.c')
0 files changed, 0 insertions, 0 deletions