RISC-V: Introduce vfloat16m{f}*_t and their machine mode.

This patch would like to introduce the built-in type vfloat16m{f}*_t, as
well as their machine mode VNx*HF. They depend on architecture zvfhmin
or zvfh.

When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will
be true.

The underlying PATCH will implement the zvfhmin extension based on this.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
	and zvfh.
	* config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
	(main): Disable FP16 tuple.
	* config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
	(TARGET_VECTOR_ELEN_FP_16): Ditto.
	* config/riscv/riscv-vector-builtins.cc (check_required_extensions):
	Add FP16.
	* config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
	(vfloat16mf2_t): Ditto.
	(vfloat16m1_t): Ditto.
	(vfloat16m2_t): Ditto.
	(vfloat16m4_t): Ditto.
	(vfloat16m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
	New macro.
	* config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
	machine mode based on TARGET_VECTOR_ELEN_FP_16.

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