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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-12-10 16:32:40 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-12-10 16:32:40 +0000 |
| commit | 30f8bf3d6c072a8fce14e8a003dff485a9068a97 (patch) | |
| tree | 3c677c1d911f9af6a7ecf2f90f1d00705af35e7c /gcc/fortran/misc.c | |
| parent | 393283b8efaba009ce57a78fa658f55fbf262551 (diff) | |
| download | gcc-30f8bf3d6c072a8fce14e8a003dff485a9068a97.zip gcc-30f8bf3d6c072a8fce14e8a003dff485a9068a97.tar.gz gcc-30f8bf3d6c072a8fce14e8a003dff485a9068a97.tar.bz2 | |
[AArch64] Fix INDEX patterns for partial VNx2 modes
The INDEX patterns handle partial modes by choosing the container
size rather than the element size, so that the number of lanes
(and thus number of additions) matches the mode. This means that
all VNx4 modes use .s and all VNx2 modes use .d, etc.
When adding this, I'd forgotten that the choice between Wn and Xn
registers would need to be updated to use the container size too.
For partial VNx2s, we were using .d containers with Wn rather than
Xn source registers.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (vccore): New iterator.
* config/aarch64/aarch64-sve.md (vec_series<mode>): Use it instead
of vwcore.
(*vec_series<mode>_plus): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/mixed_size_6.c: New test.
From-SVN: r279173
Diffstat (limited to 'gcc/fortran/misc.c')
0 files changed, 0 insertions, 0 deletions