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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-03-08 17:46:40 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-03-08 17:50:51 +0000 |
| commit | 796f5220c808bc37adbd1081476589ab1a5d7ac3 (patch) | |
| tree | 6aced8f7717aec1f6bc765875b7c90d201a91b38 /gcc/fortran/frontend-passes.cc | |
| parent | 6319391d5634ceb07abfadfaabee25e403f5110a (diff) | |
| download | gcc-796f5220c808bc37adbd1081476589ab1a5d7ac3.zip gcc-796f5220c808bc37adbd1081476589ab1a5d7ac3.tar.gz gcc-796f5220c808bc37adbd1081476589ab1a5d7ac3.tar.bz2 | |
arm: MVE: Relax addressing modes for full loads and stores
This patch relaxes the addressing modes for the mve full load and stores (by
full loads and stores I mean non-widening or narrowing loads and stores resp).
The code before was requiring a LO_REGNUM for these, where this is only a
requirement if the load is widening or the store narrowing.
gcc/ChangeLog:
PR target/104790
* config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
* config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on base
register for non widening loads or narrowing stores.
Diffstat (limited to 'gcc/fortran/frontend-passes.cc')
0 files changed, 0 insertions, 0 deletions