RISC-V: Bugfix for legitimize move when get vec mode in zve32f

If we want to extract 64bit value but ELEN < 64, we use RVV
vector mode with EEW = 32 to extract the highpart and lowpart.
However, this approach doesn't honor DFmode when movdf pattern
when ZVE32f and of course results in ICE when zve32f.

This patch would like to reuse the approach with some additional
handing, consider lowpart bits is meaningless for FP mode, we need
one int reg as bridge here. For example:

rtx tmp = gen_rtx_reg (DImode)
reg:DI = reg:DF (fmv.d.x) // Move DF reg to DI
...
perform the extract for high and low parts
...
reg:DF = reg:DI (fmv.x.d) // Move DI reg back to DF after all done

	PR target/112743

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Take the
	exist (U *mode) and handle DFmode like DImode when EEW is
	32bits for ZVE32F.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112743-2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

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